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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id q8-20020a2e9688000000b002bcdbfe36b9sm38083lji.111.2023.11.22.12.09.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Nov 2023 12:09:57 -0800 (PST) Message-ID: <90885d90-2e25-404b-b3a3-13d134801146@linaro.org> Date: Wed, 22 Nov 2023 21:09:54 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 2/4] clk: qcom: branch: Add mem ops support for branch2 clocks Content-Language: en-US To: Imran Shaik , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Ajit Pandey , Jagadeesh Kona References: <20231117095558.3313877-1-quic_imrashai@quicinc.com> <20231117095558.3313877-3-quic_imrashai@quicinc.com> From: Konrad Dybcio In-Reply-To: <20231117095558.3313877-3-quic_imrashai@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/17/23 10:55, Imran Shaik wrote: > From: Taniya Das > > Add the support for mem ops implementation to handle the sequence of > enable/disable of the memories in ethernet PHY, prior to enable/disable > of the respective clocks, which helps retain the respecive block's > register contents. > > Signed-off-by: Taniya Das > Signed-off-by: Imran Shaik > --- > drivers/clk/qcom/clk-branch.c | 39 +++++++++++++++++++++++++++++++++++ > drivers/clk/qcom/clk-branch.h | 21 +++++++++++++++++++ > 2 files changed, 60 insertions(+) > > diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c > index fc4735f74f0f..61bdd2147bed 100644 > --- a/drivers/clk/qcom/clk-branch.c > +++ b/drivers/clk/qcom/clk-branch.c > @@ -1,6 +1,7 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > * Copyright (c) 2013, The Linux Foundation. All rights reserved. > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #include > @@ -134,6 +135,44 @@ static void clk_branch2_disable(struct clk_hw *hw) > clk_branch_toggle(hw, false, clk_branch2_check_halt); > } > > +static int clk_branch2_mem_enable(struct clk_hw *hw) > +{ > + struct clk_mem_branch *mem_br = to_clk_mem_branch(hw); > + struct clk_branch branch = mem_br->branch; > + const char *name = clk_hw_get_name(&branch.clkr.hw); Bit of a microoptimization, but adding this implicitly in the WARN would only execute clk_hw_get_name when necessary > + u32 val; > + int ret; > + > + regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg, > + mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask); It's quite a nit from me, but it would be nice to have the next line aligned with the opening brace (with a tab size of 8) Konrad