From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751304AbdEBPYM (ORCPT ); Tue, 2 May 2017 11:24:12 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6349 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750763AbdEBPYJ (ORCPT ); Tue, 2 May 2017 11:24:09 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 02 May 2017 08:24:09 -0700 Subject: Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout To: Laxman Dewangan , References: <1493733937-15822-1-git-send-email-ldewangan@nvidia.com> CC: , , From: Jon Hunter Message-ID: <908ed0dc-2a75-4348-357c-191fa7348974@nvidia.com> Date: Tue, 2 May 2017 16:23:24 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <1493733937-15822-1-git-send-email-ldewangan@nvidia.com> X-Originating-IP: [10.21.132.162] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/05/17 15:05, Laxman Dewangan wrote: > The PWM hardware IP is taped-out with different maximum frequency > on different SoCs. > > From HW team: > Before Tegra186, it is 38.4MHz. > In Tegra186, it is 102MHz. > > Add support to limit the clock source frequency to the maximum IP > supported frequency. Provide these values via SoC chipdata. > > Signed-off-by: Laxman Dewangan > > --- > Changes from V1: > - Set the 48MHz maximum frequency for Tegra210 and earlier. I think that your changelog needs to be updated, because it still says 38.4MHz and not 48MHz. Cheers Jon -- nvpublic