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Fri, 06 Nov 2026 02:36:44 -0800 (PST) Received: from [10.217.219.8] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b0d7c66fe1sm2885209a91.7.2026.11.06.02.36.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Nov 2026 02:36:43 -0800 (PST) Message-ID: <90ad258b-00f3-45b2-bf7d-5865a9d66258@oss.qualcomm.com> Date: Fri, 6 Nov 2026 16:06:38 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: mmc: sdhci-msm: Document bindings for Nord SDCC To: Krzysztof Kozlowski Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shazad Hussain , Manivannan Sadhasivam , Nitin Rawat , Ram Gupta References: <20261102-sdcc_scmi-v1-0-244dbd893051@oss.qualcomm.com> <20261102-sdcc_scmi-v1-1-244dbd893051@oss.qualcomm.com> <20261104-sticky-perch-from-sirius-d3ebb3@quoll> Content-Language: en-US From: Anjana Hari In-Reply-To: <20261104-sticky-perch-from-sirius-d3ebb3@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDA0MiBTYWx0ZWRfXylZv/fyk3m57 rHN4+mfJt9tLJnmIrRAShoSadH4RJ1rPATY2Sp00TCRjZwUpYvyV80/lUyG+Du7IbHpPsdY9ZW3 SVxWS8+CFpW4cZm1p/kB/Huff05DQNRlLQZaEqUshaVk41RKKgbEI/od0Q+cuHMpAUNp2/Y/Py8 8b8zNYl8rOk3/+xCYzAcpVNYxqp3zILsrrKIF6JCyuxJVaq4wwNcz/gUNMYXDyjBrdOoDC0CTBz nxo5KMDH9UVZ36Dwtz9LxtaSQ7zsDiQrHJEhajnO4OkIN7hod0olx7Y8fPyhYTVMJ4iyL3BznPq 1CzHk4LgqXMkaU9YknQ2CwvtK5/E82eg4K/E8wKwCGVTTh3DvfV9STaFPat31VTQSlKna9ZR4bq I6QyPb72vVdjhKJOoqcEIxJpl+8sWQKmfdi5Y71GKvschFALmFh8+bZ8i1nfSqPXfdUCI37HRZF 1nJkml3t+alY8CeWBFw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDA0MiBTYWx0ZWRfXyzBoexjJsgcK P8D8u2g7o7AyDEb9z5nVtmXV6500+OMfPb2mkwPZfBQ1utvv6B6vcWnE4X9VK2tz1/mwR4lll4B 8W5gpa4WNAszmio4PTpV6cRUPBYAym8= X-Proofpoint-ORIG-GUID: zpVzN5z1uKfnFszMYFsLfplUW57fwG2J X-Authority-Analysis: v=2.4 cv=GpzXaU1C c=1 sm=1 tr=0 ts=6aedadbe cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=P-IC7800AAAA:8 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=f_B6lkSkO6dyqIEesxIA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=d3PnA9EDa4IxuAV0gXij:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: zpVzN5z1uKfnFszMYFsLfplUW57fwG2J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_03,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 malwarescore=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060042 On 11/4/2026 7:28 PM, Krzysztof Kozlowski wrote: > On Mon, Nov 02, 2026 at 07:33:41PM +0530, Anjana Hari wrote: >> Add Device Tree binding for the Nord SDHCI variant of the Qualcomm >> sdhci-msm controller, where platform resources are managed by firmware >> through the SCMI power protocol rather than being directly accessible >> to Linux. > > A nit, subject: drop second/last, redundant "bindings". The > "dt-bindings" prefix is already stating that these are bindings. > See also: > https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23 > Acked, will address in the upcoming v2 patch.>> >> Unlike existing sdhci-msm variants, this binding does not require >> clock, interconnect, reset, or regulator properties. Instead, platform >> resource control is abstracted behind two logical power domains: >> >> - "power": controls the SDCC rail power state. The kernel requests >> power-on and power-off transitions via the runtime PM framework; >> these are forwarded to firmware as SCMI power-state messages. >> >> - "perf": exposes the supported clock frequencies as OPPs populated >> dynamically by the SCMI perf domain driver at probe time via the >> SCMI performance protocol. The driver selects operating points via >> dev_pm_opp_find_freq_floor() and dev_pm_opp_set_opp(). >> >> Both domains must be listed under power-domains with their names >> declared in power-domain-names. >> >> The compatible string "qcom,nord-sdhci" selects this variant at probe >> time and causes the driver to attach the two power domains via >> dev_pm_domain_attach_list() with PD_FLAG_DEV_LINK_ON, ensuring correct >> suspend/resume ordering between the SDCC controller and the firmware >> power domain devices. > > Do not describe driver. How is it exactly relevant here for the hardware > description? > Agreed, will be addressed.>> >> Signed-off-by: Anjana Hari >> --- >> .../devicetree/bindings/mmc/qcom,nord-sdhci.yaml | 89 ++++++++++++++++++++++ >> 1 file changed, 89 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/mmc/qcom,nord-sdhci.yaml b/Documentation/devicetree/bindings/mmc/qcom,nord-sdhci.yaml >> new file mode 100644 >> index 000000000000..c512628617b0 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mmc/qcom,nord-sdhci.yaml >> @@ -0,0 +1,89 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mmc/qcom,nord-sdhci.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Nord SDHCI Controller >> + >> +maintainers: >> + - Anjana Hari >> + >> +description: >> + SDHCI (SD Host Controller Interface) present on Qualcomm Nord SoC. >> + Clock and power resources are managed by firmware through an SCMI >> + server, so no clock entries are required in the device tree node. >> + >> +properties: >> + compatible: >> + const: qcom,nord-sdhci >> + >> + reg: >> + maxItems: 1 >> + >> + reg-names: >> + items: >> + - const: hc > > Where is CQHCI? > >> + >> + interrupts: >> + maxItems: 2 >> + >> + interrupt-names: >> + items: >> + - const: hc_irq >> + - const: pwr_irq >> + >> + iommus: >> + maxItems: 1 >> + description: phandle to the apps SMMU node with SID mask. > > Drop description > >> + >> + dma-coherent: true >> + >> + power-domains: >> + maxItems: 2 >> + >> + power-domain-names: >> + items: >> + - const: power >> + - const: perf > > Best regards, > Krzysztof