From: Andrew Lunn <andrew@lunn.ch>
To: MD Danish Anwar <danishanwar@ti.com>
Cc: Rob Herring <robh@kernel.org>, Roger Quadros <rogerq@ti.com>,
Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paolo Abeni <pabeni@redhat.com>, Jakub Kicinski <kuba@kernel.org>,
Eric Dumazet <edumazet@google.com>,
"David S. Miller" <davem@davemloft.net>,
Vignesh Raghavendra <vigneshr@ti.com>,
Simon Horman <horms@kernel.org>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
netdev@vger.kernel.org, srk@ti.com, r-gunasekaran@ti.com,
Roger Quadros <rogerq@kernel.org>
Subject: Re: [PATCH net-next v2 1/2] dt-bindings: net: Add documentation for Half duplex support.
Date: Tue, 12 Sep 2023 17:16:44 +0200 [thread overview]
Message-ID: <90b3e6cc-7246-4d02-bd0f-2ce7847bc261@lunn.ch> (raw)
In-Reply-To: <0c23d883-0a79-ee7c-332c-c6580f8691df@ti.com>
> Sure Rob, I will change the description to below.
>
> description:
> Indicates that the PHY output pin (COL) is routed to ICSSG GPIO
The PHY has multiple output pins, so i would not put COL in brackets,
but make it explicit which pin you are referring to.
> pin (PRGx_PRU0/1_GPIO10) as input and ICSSG MII port is capable
> of half duplex operations.
"input and so the ICSSG MII port is"
Andrew
next prev parent reply other threads:[~2023-09-12 15:17 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-11 6:01 [PATCH net-next v2 0/2] Add Half Duplex support for ICSSG Driver MD Danish Anwar
2023-09-11 6:01 ` [PATCH net-next v2 1/2] dt-bindings: net: Add documentation for Half duplex support MD Danish Anwar
2023-09-11 16:46 ` Rob Herring
2023-09-12 5:55 ` MD Danish Anwar
2023-09-12 15:16 ` Andrew Lunn [this message]
2023-09-13 6:17 ` [EXTERNAL] " MD Danish Anwar
2023-09-14 10:35 ` Simon Horman
2023-09-11 6:02 ` [PATCH net-next v2 2/2] net: ti: icssg-prueth: Add support for half duplex operation MD Danish Anwar
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