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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-60fcb0c9236sm9444279a12.46.2025.07.09.14.24.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Jul 2025 14:24:11 -0700 (PDT) Message-ID: <90d21fe5-97f6-40e6-98e5-378a7809e8dc@oss.qualcomm.com> Date: Wed, 9 Jul 2025 23:24:09 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 3/3] ufs: ufs-qcom: Enable QUnipro Internal Clock Gating To: Nitin Rawat , Avri Altman , "mani@kernel.org" , "James.Bottomley@HansenPartnership.com" , "martin.petersen@oracle.com" , "bvanassche@acm.org" , "avri.altman@wdc.com" , "ebiggers@google.com" , "neil.armstrong@linaro.org" Cc: "linux-arm-msm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-scsi@vger.kernel.org" References: <20250708212534.20910-1-quic_nitirawa@quicinc.com> <20250708212534.20910-4-quic_nitirawa@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=ZJ/XmW7b c=1 sm=1 tr=0 ts=686eddff cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=NCvSw6eEAai3H5U51bMA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: clw4v-MbEvBpAZp4ruhkMAzalO96ztDg X-Proofpoint-GUID: clw4v-MbEvBpAZp4ruhkMAzalO96ztDg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzA5MDE5MiBTYWx0ZWRfX21OwrKAgnNS+ T+Pkl6yIn6J9GQXblUi0KtYr3xpcul/APWt0aaXRbk8o1yBX7xdKZALj47KlvyY3n+/SQiHoeyR 87tqxBMOuwyvGly4oTguLdEoUon2JYdeK/vv72cH0fS/aX/1n+0uw44gjm3S6aI3Ks0dwBFz9hY kJs5D2ZCBbbZisZm+5P227MY5nkIU4M8UGh4E2xYNdSs3l4mcZtZaLrhFlMnxV2VEM+2RJLS8Ec 3m/+N96lWH2b/y2JYZU4UhbjFyWBgB29mC25ggzefaRPx9BwqUWjp9w7Ls2QZHBnChaXJM0mSBh wpcmDHrLqZXVDJT3Wgd/IiJ9hd5MMnVn7m8O7HUDiyQMHd7rs42yK+vbPvVsCuafw0eupPrh6JQ fulTvl8lLJz/q3eTHXm0oxiNCPMNvFuiPUZzXB7DRnaiEB2g5JaBZ8UpC9RUhISnU27Y9N42 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-09_05,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=758 impostorscore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 phishscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507090192 On 7/9/25 11:13 PM, Nitin Rawat wrote: > > > On 7/9/2025 10:46 AM, Avri Altman wrote: >>> Enable internal clock gating for QUnipro by setting the following attributes to 1 >>> during host controller initialization: >>> - DL_VS_CLK_CFG >>> - PA_VS_CLK_CFG_REG >>> - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN >>> >>> This change is necessary to support the internal clock gating mechanism in >>> Qualcomm UFS host controller. This is power saving feature and hence driver >>> can continue to function correctly despite any error in enabling these feature. >> Does this change offloads clock gating? >> i.e. no need to set UFSHCD_CAP_CLK_GATING ? > No , this change does not offload sw based UFS clock gating. Host controller has its own internal clock gating mechanism Does QUnipro == "the UFS controller found on Qualcomm platforms"? If so, please use some version of the latter name to make it more easily discernible Konrad