Re: [PATCH v6 3/4] i2c: tegra: Add logic to support different register offsets

[Kartik Rajput <kkartik@nvidia.com>]

On 13/01/26 18:04, Jon Hunter wrote:
> 
> On 13/01/2026 09:04, Kartik Rajput wrote:
>> Tegra410 use different offsets for existing I2C registers, update
>> the logic to use appropriate offsets per SoC.
>>
>> As the registers offsets are now also defined for dvc and vi, following
>> function are not required and they are removed:
>>   - tegra_i2c_reg_addr(): No translation required.
>>   - dvc_readl(): Replaced with i2c_readl().
>>
>> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
>> ---
>> Changes in v6:
>>     * Do not remove dvc_writel().
>>     * Keep DVC registers defined as a macro.
>>     * Correct Tegra20 DVC register offsets.
>>     * Remove sl_cnfg, sl_addr1 and sl_addr2 registers for DVC and VI
>>       as they are not used.
>> Changes in v2:
>>     * Replace individual is_dvc and is_vi flags with an I2C variant.
>>     * Add tegra20_dvc_i2c_hw and tegra210_vi_i2c_hw in a separate
>>       patch.
>>     * Use calculated offsets for tegra20_dvc_i2c_regs and
>>       tegra210_vi_i2c_regs.
>>     * Initialize registers only if they are used on the given SoC.
>> ---
>>   drivers/i2c/busses/i2c-tegra.c | 368 +++++++++++++++++++++------------
>>   1 file changed, 239 insertions(+), 129 deletions(-)
> 
> ...
> 
>>   static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
>> @@ -1937,6 +2045,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
>>       .enable_hs_mode_support = true,
>>       .has_mutex = true,
>>       .variant = TEGRA_I2C_VARIANT_DEFAULT,
>> +    .regs = &tegra20_i2c_regs,
>>   };
> 
> 
> Is this correct? Tegra256 sets 'has_mutex' to true but is using the tegra20_i2c_regs which does not define the 'sw_mutex' register.
> 
> Jon
> 

Hi Jon,

Yes, this is incorrect, we should be using tegra264_i2c_regs here. I will fix this in the next patch set.

Thanks,
Kartik