Re: [PATCH v7 0/7] Add initial USB support for the Renesas RZ/G3S SoC

[Claudiu Beznea <claudiu.beznea@tuxon.dev>]

Hi,

Gentle ping. Apart from Geert's comment, could you please let me know if
there are other comments on this series?

Thank you,
Claudiu

On 9/25/25 13:02, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Hi,
> 
> Series adds initial USB support for the Renesas RZ/G3S SoC.
> 
> Series is split as follows:
> - patches 1-2/7		- fixes on bindings and driver for USB PHY
> - patches 3-5/7		- updates the rzg2l-usbphy-ctrl driver and documentation
> 			  with support for setting PWRRDY though SYSC
> - patches 6-7/7		- add device tree support
> 
> Merge strategy, if any:
> - patches 1-2/7 can go through the PHY tree
> - patches 3-5/7 can go through the reset tree
> - patches 6-7/7 can go through Renesas tree
> 
> Thank you,
> Claudiu Beznea
> 
> Changes in v7:
> - used proper regmap update value for PWRRDY
> - collected tags
> - dropped Tb tags from dt-bindings
> 
> Changes in v6:
> - in patch 2/7 dropped the struct rcar_gen3_chan::rstc as it is not
>   used anymore
> - in patch 4/7 used syscon_regmap_lookup_by_phandle_args()
> - collected tags
> 
> Changes in v5:
> - dropped patch "soc: renesas: rz-sysc: Add syscon/regmap support" as it
>   already modified and pubished also at [2] with the latest review comments
>   addressed
> - fixed the documentation
> 
> Changes in v4:
> - replaced "renesas,sysc-signals" DT property with "renesas,sysc-pwrrdy"
> - dropped the "renesas,sysc-signals" property from USB PHY (as proposed
>   in v3) and let only the USB PHY CTRL driver to handle it as on RZ/G3S
>   the USB PHY CTRL driver needs to be probed before any other USB driver
> - dropped the signal abstraction from SYSC driver as there is no need
>   for reference counting it now
> - adjusted the "soc: renesas: rz-sysc: Add syscon/regmap support" to
>   comply with the latest review comments
> 
> Changes in v3:
> - as the basics of the SYSC driver was integrated, only the signal support
>   was preserved in this series, in a separate patch; patch 01/12 was
>   adjusted (by addressing the review comments received at [1]) as it is
>   necessary to build the signal support on top of it
> - after long discussions with the internal HW team it has been confirmed
>   that the relation b/w individual USB specific HW blocks and signals
>   is like:
> 
>                                    ┌──────────────────────────────┐
>                                    │                              │◄── CPG_CLKON_USB.CLK0_ON
>                                    │     USB CH0                  │
>     ┌──────────────────────────┐   │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK2_ON
>     │                 ┌────────┐   ││host controller registers  │ │
>     │                 │        │   ││function controller registers│
>     │                 │ PHY0   │◄──┤└───────────────────────────┘ │
>     │     USB PHY     │        │   └────────────▲─────────────────┘
>     │                 └────────┘                │
>     │                          │    CPG_BUS_PERI_COM_MSTOP.MSTOP{6, 5}_ON
>     │┌──────────────┐ ┌────────┐
>     ││USBPHY control│ │        │
>     ││  registers   │ │ PHY1   │   ┌──────────────────────────────┐
>     │└──────────────┘ │        │◄──┤     USB CH1                  │
>     │                 └────────┘   │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK1_ON
>     └─▲───────▲─────────▲──────┘   ││ host controller registers │ │
>       │       │         │          │└───────────────────────────┘ │
>       │       │         │          └────────────▲─────────────────┘
>       │       │         │                       │
>       │       │         │           CPG_BUS_PERI_COM_MSTOP.MSTOP7_ON
>       │PWRRDY │         │
>       │       │   CPG_CLK_ON_USB.CLK3_ON
>       │       │
>       │  CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON
>       │
>     ┌────┐
>     │SYSC│
>     └────┘
> 
>   where:
>   - CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X
>       of different USB blocks, X in {0, 1, 2, 3}
>   - CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the
>     MSTOP of different USB blocks, X in {4, 5, 6, 7}
>   - USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used
>     by the USB CH0, USB CH1
>   - SYSC is the system controller block controlling the PWRRDY signal
>   - USB CHx are individual USB block with host and function capabilities
>     (USB CH0 have both host and function capabilities, USB CH1 has only
>     host capabilities)
> 
>   Due to this, the PWRRDY signal was also passed to the reset-rzg2l-usbphy-ctrl
>   reset driver (as it controls the USBPHY control registers) and these
>   are in the USB PHY block controlled by PWRRDY signal.
> 
>   The PWRRDY signal need to be de-asserted on probe before enabling the module
>   clocks and the module MSTOP. To avoid any violation of this configuration
>   sequence, the PWRRDY signal is now controlled by USB PHY driver and the
>   reset-rzg2l-usbphy-ctrl driver.
> 
>   As the PHYs gets reset signals from the USB reset controller driver, the
>   reset-rzg2l-usbphy-ctrl is probed before the USB PHY driver and thus,
>   in theory, we can drop the signal support (reference counting of the
>   USB PWRRDY) and configure the USB PWRRDY just in the reset-rzg2l-usbphy-ctrl.
> 
>   However, to have a proper description of the diagram described above in 
>   device tree and ensure the configuration sequence b/w PRWRDY, CLK and MSTOP
>   is preserved, the PWRRDY signal is controlled in this series in all the
>   drivers that work with registers from the USB PHY block.
> 
>   Please provide your feedback on this solution.
> 
> Thank you,
> Claudiu
> 
> [1] https://lore.kernel.org/all/20250330214945.185725-2-john.madieu.xa@bp.renesas.com/
> [2] https://lore.kernel.org/all/20250818162859.9661-2-john.madieu.xa@bp.renesas.com/
> 
> Changes in v2:
> - dropped v1 patches already applied
> - added fixes patches (07/14 and 09/14)
> - dropped the approach of handling the USB PWRRDY though a reset controller
>   driver and introduced the signal concept for the SYSC driver; because
>   of this, most of the work done in v1 was dropped
> - per patch changes are listed in individual patches, if any
> 
> Christophe JAILLET (1):
>   phy: renesas: rcar-gen3-usb2: Fix an error handling path in
>     rcar_gen3_phy_usb2_probe()
> 
> Claudiu Beznea (6):
>   dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S
>   dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
>   reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
>   reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
>   arm64: dts: renesas: r9a08g045: Add USB support
>   arm64: dts: renesas: rzg3s-smarc: Enable USB support
> 
>  .../bindings/phy/renesas,usb2-phy.yaml        |   1 +
>  .../reset/renesas,rzg2l-usbphy-ctrl.yaml      |  41 +++++-
>  arch/arm64/boot/dts/renesas/r9a08g045.dtsi    | 118 ++++++++++++++++++
>  arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi  |  57 +++++++++
>  drivers/phy/renesas/phy-rcar-gen3-usb2.c      |  20 ++-
>  drivers/reset/Kconfig                         |   1 +
>  drivers/reset/reset-rzg2l-usbphy-ctrl.c       |  66 ++++++++++
>  7 files changed, 292 insertions(+), 12 deletions(-)
>