From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m93188.xmail.ntesmail.com (mail-m93188.xmail.ntesmail.com [103.126.93.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A98334C83C for ; Wed, 3 Jun 2026 01:28:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=103.126.93.188 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780450139; cv=none; b=qLURsm42nCo4x/dL7YvATnsIbESo0pE91RmIIo3RiQia1DHX8SNFtrw/uLW4/o8LNiIf9plPCEhunjp3vnU6YaLtHv4/QljHor1i1WKks47K8ok1VBiF/zNMk6a96Sk/U2X9BMIT0F9h5w0jC8Ffj23+1pyR1kRVI3UHPJNkMqM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780450139; c=relaxed/simple; bh=FqjM2glmKYW5WZDACFvQDsiNv0z0P0k+SwGfjcQe4TI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=d1DZEK6HI6zDg211zRrz7/uFRAbXWWwWW2liVgYosukl64hFf/Z5X46L4D1rFBVGX45Hom2WgKnFubxwMGddCWfXW72mGEoLdFVKY6kG16IVdRkhTt7ju4hkObQFJXrc6rExmiuxCyl0b6maGd3Ax+feYruqxkeC2iawGYh8owE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=DpCRBhYh; arc=none smtp.client-ip=103.126.93.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="DpCRBhYh" Received: from [172.16.12.90] (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 40d472abe; Wed, 3 Jun 2026 09:28:46 +0800 (GMT+08:00) Message-ID: <91378132-8a8e-4bcc-9aa7-4de9fb135a6a@rock-chips.com> Date: Wed, 3 Jun 2026 09:28:44 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] drm/rockchip: dsi: Add maximum per lane bit rate calculation To: Heiko Stuebner Cc: Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Guochun Huang , Chaoyi Chen , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260324085838.90-1-kernel@airkyi.com> <4888940.6M6d0yLqnL@phil> Content-Language: en-US From: Chaoyi Chen In-Reply-To: <4888940.6M6d0yLqnL@phil> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9e8b18ebda03a7kunma7a4b39932116e X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkaTU1NVktKGkhCGUhOSkodQ1YVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU 9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=DpCRBhYhHsk59imJ+FGOLy8d4MOtCjg9bDkKtXvNrDk5iWWBwZS1A4x0JDviW1oUGeFdDFS2d0NWdJVtU4YkUlRC3PajKAKdjolU8I8op2P1QcWAmkz2FKNW1VnFI1EwqOqeverIZpow5QyF0+1N/oei5IaiUWhLDi9TV/7d7fg=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=m1cnttQcMrvUZx5o8JPHBR3oI+NYB+tDa2bCbLIj358=; h=date:mime-version:subject:message-id:from; Hi Heiko, On 6/3/2026 4:59 AM, Heiko Stuebner wrote: > Am Dienstag, 24. März 2026, 09:58:37 Mitteleuropäische Sommerzeit schrieb Chaoyi Chen: >> From: Chaoyi Chen >> >> Different chips have varying support for the maximum bit rate per lane. >> >> Add calculation for the maximum per lane bit rate for various chip >> platforms, and relax the bandwidth margin requirements. >> >> Signed-off-by: Chaoyi Chen >> --- >> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 21 +++++++++++++++---- >> 1 file changed, 17 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c >> index 3547d91b25d3..d3bacfae174e 100644 >> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c >> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c >> @@ -268,6 +268,7 @@ struct rockchip_dw_dsi_chip_data { >> >> unsigned int flags; >> unsigned int max_data_lanes; >> + unsigned long max_bit_rate_per_lane; >> }; >> >> struct dw_mipi_dsi_rockchip { >> @@ -565,7 +566,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, >> int bpp; >> unsigned long mpclk, tmp; >> unsigned int target_mbps = 1000; >> - unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; >> + unsigned int max_mbps; >> unsigned long best_freq = 0; >> unsigned long fvco_min, fvco_max, fin, fout; >> unsigned int min_prediv, max_prediv; >> @@ -573,6 +574,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, >> unsigned long _fbdiv, best_fbdiv; >> unsigned long min_delta = ULONG_MAX; >> >> + max_mbps = dsi->cdata->max_bit_rate_per_lane; > > I may be blind, but how do the values come together? > In the dppa_map table we have mbps values of 89 to 1500 > (MHz) > > While below the values set are > .max_bit_rate_per_lane = 1500000000UL, > in Hz I guess > > And I don't see the needed conversion somehow. > > Oh! It should be: max_mbps = dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC; Will fix in v2. >> dsi->format = format; >> bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); >> if (bpp < 0) { >> @@ -584,8 +586,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, >> >> mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); >> if (mpclk) { >> - /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ >> - tmp = mpclk * (bpp / lanes) * 10 / 8; >> + /* take 1 / 0.9, since mbps must big than bandwidth of RGB */ >> + tmp = mpclk * (bpp / lanes) * 10 / 9; > > Please do this in a separate patch, especially as I would expect some > sort of explanation on why this is ok to do. > Sure! I'll split this out in the new series. -- Best, Chaoyi