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Sun, 5 Apr 2020 06:37:33 +0000 (UTC) Received: from [10.36.112.58] (ovpn-112-58.ams2.redhat.com [10.36.112.58]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6078E10013D9; Sun, 5 Apr 2020 06:37:27 +0000 (UTC) Subject: Re: [PATCH v11 06/10] iommu/vt-d: Support flushing more translation cache types To: Jacob Pan , Lu Baolu , iommu@lists.linux-foundation.org, LKML , Joerg Roedel , David Woodhouse , Jean-Philippe Brucker Cc: Yi Liu , "Tian, Kevin" , Raj Ashok , Alex Williamson , Christoph Hellwig , Jonathan Cameron References: <1585939334-21396-1-git-send-email-jacob.jun.pan@linux.intel.com> <1585939334-21396-7-git-send-email-jacob.jun.pan@linux.intel.com> From: Auger Eric Message-ID: <913838c1-6ae0-c349-dafe-1ea816e4139a@redhat.com> Date: Sun, 5 Apr 2020 08:37:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: <1585939334-21396-7-git-send-email-jacob.jun.pan@linux.intel.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jacob, On 4/3/20 8:42 PM, Jacob Pan wrote: > When Shared Virtual Memory is exposed to a guest via vIOMMU, scalable > IOTLB invalidation may be passed down from outside IOMMU subsystems. > This patch adds invalidation functions that can be used for additional > translation cache types. > > Signed-off-by: Jacob Pan Reviewed-by: Eric Auger Thanks Eric > > --- > v9 -> v10: > Fix off by 1 in pasid device iotlb flush > > Address v7 missed review from Eric > > --- > > Signed-off-by: Jacob Pan > --- > drivers/iommu/dmar.c | 36 ++++++++++++++++++++++++++++++++++++ > drivers/iommu/intel-pasid.c | 3 ++- > include/linux/intel-iommu.h | 20 ++++++++++++++++---- > 3 files changed, 54 insertions(+), 5 deletions(-) > > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c > index f77dae7ba7d4..4d6b7b5b37ee 100644 > --- a/drivers/iommu/dmar.c > +++ b/drivers/iommu/dmar.c > @@ -1421,6 +1421,42 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, > qi_submit_sync(&desc, iommu); > } > > +/* PASID-based device IOTLB Invalidate */ > +void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, > + u32 pasid, u16 qdep, u64 addr, unsigned size_order, u64 granu) > +{ > + unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1); > + struct qi_desc desc = {.qw2 = 0, .qw3 = 0}; > + > + desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) | > + QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | > + QI_DEV_IOTLB_PFSID(pfsid); > + desc.qw1 = QI_DEV_EIOTLB_GLOB(granu); > + > + /* > + * If S bit is 0, we only flush a single page. If S bit is set, > + * The least significant zero bit indicates the invalidation address > + * range. VT-d spec 6.5.2.6. > + * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB. > + * size order = 0 is PAGE_SIZE 4KB > + * Max Invs Pending (MIP) is set to 0 for now until we have DIT in > + * ECAP. > + */ > + desc.qw1 |= addr & ~mask; > + if (size_order) > + desc.qw1 |= QI_DEV_EIOTLB_SIZE; > + > + qi_submit_sync(&desc, iommu); > +} > + > +void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, int pasid) > +{ > + struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0}; > + > + desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) | QI_PC_GRAN(granu) | QI_PC_TYPE; > + qi_submit_sync(&desc, iommu); > +} > + > /* > * Disable Queued Invalidation interface. > */ > diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c > index fcd015644c4f..698e661ccca7 100644 > --- a/drivers/iommu/intel-pasid.c > +++ b/drivers/iommu/intel-pasid.c > @@ -435,7 +435,8 @@ pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, > { > struct qi_desc desc; > > - desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid); > + desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) | > + QI_PC_PASID(pasid) | QI_PC_TYPE; > desc.qw1 = 0; > desc.qw2 = 0; > desc.qw3 = 0; > diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h > index a5bd53cf190c..f775bb825343 100644 > --- a/include/linux/intel-iommu.h > +++ b/include/linux/intel-iommu.h > @@ -334,7 +334,7 @@ enum { > #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4)) > #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK) > #define QI_IOTLB_IH(ih) (((u64)ih) << 6) > -#define QI_IOTLB_AM(am) (((u8)am)) > +#define QI_IOTLB_AM(am) (((u8)am) & 0x3f) > > #define QI_CC_FM(fm) (((u64)fm) << 48) > #define QI_CC_SID(sid) (((u64)sid) << 32) > @@ -353,16 +353,21 @@ enum { > #define QI_PC_DID(did) (((u64)did) << 16) > #define QI_PC_GRAN(gran) (((u64)gran) << 4) > > -#define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0)) > -#define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1)) > +/* PASID cache invalidation granu */ > +#define QI_PC_ALL_PASIDS 0 > +#define QI_PC_PASID_SEL 1 > > #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) > #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) > -#define QI_EIOTLB_AM(am) (((u64)am)) > +#define QI_EIOTLB_AM(am) (((u64)am) & 0x3f) > #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) > #define QI_EIOTLB_DID(did) (((u64)did) << 16) > #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) > > +/* QI Dev-IOTLB inv granu */ > +#define QI_DEV_IOTLB_GRAN_ALL 1 > +#define QI_DEV_IOTLB_GRAN_PASID_SEL 0 > + > #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) > #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) > #define QI_DEV_EIOTLB_GLOB(g) ((u64)g) > @@ -687,8 +692,15 @@ extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, > unsigned int size_order, u64 type); > extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, > u16 qdep, u64 addr, unsigned mask); > + > void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, > unsigned long npages, bool ih); > + > +extern void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, > + u32 pasid, u16 qdep, u64 addr, unsigned size_order, u64 granu); > + > +extern void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, int pasid); > + > extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu); > > extern int dmar_ir_support(void); >