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[78.11.189.27]) by smtp.googlemail.com with ESMTPSA id r12-20020a5d6c6c000000b00203ec2b1255sm1820380wrz.60.2022.03.17.08.16.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 17 Mar 2022 08:16:26 -0700 (PDT) Message-ID: <9143a2b5-8d53-9767-ea3c-d2b3555333f2@canonical.com> Date: Thu, 17 Mar 2022 16:16:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v2 1/8] dt-bindings: pinctrl: mvebu: Document bindings for AC5 Content-Language: en-US To: Andrew Lunn Cc: Chris Packham , "robh+dt@kernel.org" , "linus.walleij@linaro.org" , "catalin.marinas@arm.com" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-gpio@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" References: <20220314213143.2404162-1-chris.packham@alliedtelesis.co.nz> <20220314213143.2404162-2-chris.packham@alliedtelesis.co.nz> <4e6df448-5562-8f50-6f46-91acb279bc1a@canonical.com> <7e73bba0-8b54-772c-2e94-8fca4e4e3294@alliedtelesis.co.nz> <6d902e7d-b71f-9dcd-9175-cc706e3d60cc@alliedtelesis.co.nz> <4b1f4772-35f9-3e21-6429-b64c7427144a@canonical.com> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/03/2022 15:14, Andrew Lunn wrote: >> What do you mean "driver fails to load"? You control the driver, don't >> you? > > It is a thin wrapper around the mvebu driver, which does all the real > work. So no, Chris does not really control what the core of the driver > does. This this design still require a pinctrl to be a child of some node? > > The existing binding documentation says: > > * Marvell Armada 37xx SoC pin and gpio controller > > Each Armada 37xx SoC come with two pin and gpio controller one for > the south bridge and the other for the north bridge. > > Inside this set of register the gpio latch allows exposing some > configuration of the SoC and especially the clock frequency of the > xtal. Hence, this node is a represent as syscon allowing sharing > the register between multiple hardware block. > > > So the syscon is there to allow the clock driver to share the register > space. This makes sense. Solution here would be to add syscon compatible to pinctrl node. This parent simple-mfd+syscon node looks like a workaround to share some registers in a highly flexible way. However isn't it better to have more obvious owner of the register space (e.g. pinctrl)? IOW, if there is only one child of syscon+simple-mfd node, why not getting rid of it and making pinctrl owner of this address space? It's also simpler code. Best regards, Krzysztof