mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Maxim Levitsky <mlevitsk@redhat.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc: pbonzini@redhat.com, seanjc@google.com, joro@8bytes.org,
	jon.grimm@amd.com, wei.huang2@amd.com, terry.bowman@amd.com
Subject: Re: [RFC PATCH 05/13] KVM: SVM: Update max number of vCPUs supported for x2AVIC mode
Date: Thu, 24 Feb 2022 19:18:31 +0200	[thread overview]
Message-ID: <9143d9d24d1b169668062a18a5f49bb8cf8e877b.camel@redhat.com> (raw)
In-Reply-To: <20220221021922.733373-6-suravee.suthikulpanit@amd.com>

On Sun, 2022-02-20 at 20:19 -0600, Suravee Suthikulpanit wrote:
> xAVIC and x2AVIC modes can support diffferent number of vcpus.
> Update existing logics to support each mode accordingly.
> 
> Also, modify the maximum physical APIC ID for AVIC to 255 to reflect
> the actual value supported by the architecture.
> 
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
> ---
>  arch/x86/include/asm/svm.h | 12 +++++++++---
>  arch/x86/kvm/svm/avic.c    |  8 +++++---
>  2 files changed, 14 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
> index 7a7a2297165b..681a348a9365 100644
> --- a/arch/x86/include/asm/svm.h
> +++ b/arch/x86/include/asm/svm.h
> @@ -250,10 +250,16 @@ enum avic_ipi_failure_cause {
>  
>  
>  /*
> - * 0xff is broadcast, so the max index allowed for physical APIC ID
> - * table is 0xfe.  APIC IDs above 0xff are reserved.
> + * For AVIC, the max index allowed for physical APIC ID
> + * table is 0xff (255).
>   */
> -#define AVIC_MAX_PHYSICAL_ID_COUNT	0xff
> +#define AVIC_MAX_PHYSICAL_ID		0XFFULL
> +
> +/*
> + * For x2AVIC, the max index allowed for physical APIC ID
> + * table is 0x1ff (511).
> + */
> +#define X2AVIC_MAX_PHYSICAL_ID		0x1FFUL

Yep, physid page can't hold more entries...

This brings the inventible question of what to do when a VM has more
that 512 vCPUs...

With AVIC, since it is xapic, it would be easy - xapic supports up to
254 CPUs.

But with x2apic, there is no such restriction on max 512 CPUs,
thus it is legal to create a VM with x2apic and more that 512 CPUs,
and x2AVIC won't work well in this case.

I guess AVIC_IPI_FAILURE_INVALID_TARGET, has to be extened to support those
cases, even with loss of performance, or we need to inhibit x2AVIC.

Best regards,
	Maxim Levitsky

>  
>  #define AVIC_HPA_MASK	~((0xFFFULL << 52) | 0xFFF)
>  #define VMCB_AVIC_APIC_BAR_MASK		0xFFFFFFFFFF000ULL
> diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
> index 0040824e4376..1999076966fd 100644
> --- a/arch/x86/kvm/svm/avic.c
> +++ b/arch/x86/kvm/svm/avic.c
> @@ -195,7 +195,7 @@ void avic_init_vmcb(struct vcpu_svm *svm)
>  	vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
>  	vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
>  	vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
> -	vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
> +	vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID;
>  	vmcb->control.avic_vapic_bar = APIC_DEFAULT_PHYS_BASE & VMCB_AVIC_APIC_BAR_MASK;
>  
>  	if (kvm_apicv_activated(svm->vcpu.kvm))
> @@ -210,7 +210,8 @@ static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
>  	u64 *avic_physical_id_table;
>  	struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
>  
> -	if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
> +	if ((avic_mode == AVIC_MODE_X1 && index > AVIC_MAX_PHYSICAL_ID) ||
> +	    (avic_mode == AVIC_MODE_X2 && index > X2AVIC_MAX_PHYSICAL_ID))
>  		return NULL;
>  
>  	avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
> @@ -257,7 +258,8 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu)
>  	int id = vcpu->vcpu_id;
>  	struct vcpu_svm *svm = to_svm(vcpu);
>  
> -	if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
> +	if ((avic_mode == AVIC_MODE_X1 && id > AVIC_MAX_PHYSICAL_ID) ||
> +	    (avic_mode == AVIC_MODE_X2 && id > X2AVIC_MAX_PHYSICAL_ID))
>  		return -EINVAL;
>  
>  	if (!vcpu->arch.apic->regs)



  reply	other threads:[~2022-02-24 17:18 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-21  2:19 [RFC PATCH 00/13] Introducing AMD x2APIC Virtualization (x2AVIC) support Suravee Suthikulpanit
2022-02-21  2:19 ` [RFC PATCH 01/13] KVM: SVM: Add warning when encounter invalid APIC ID Suravee Suthikulpanit
2022-02-24 16:30   ` Maxim Levitsky
2022-02-21  2:19 ` [RFC PATCH 02/13] x86/cpufeatures: Introduce x2AVIC CPUID bit Suravee Suthikulpanit
2022-02-24 16:32   ` Maxim Levitsky
2022-02-21  2:19 ` [RFC PATCH 03/13] KVM: SVM: Detect X2APIC virtualization (x2AVIC) support Suravee Suthikulpanit
2022-02-24 16:52   ` Maxim Levitsky
2022-03-01  9:45     ` Suravee Suthikulpanit
2022-02-21  2:19 ` [RFC PATCH 04/13] KVM: SVM: Only call vcpu_(un)blocking when AVIC is enabled Suravee Suthikulpanit
2022-02-24 16:54   ` Maxim Levitsky
2022-03-01  9:59     ` Suravee Suthikulpanit
2022-02-21  2:19 ` [RFC PATCH 05/13] KVM: SVM: Update max number of vCPUs supported for x2AVIC mode Suravee Suthikulpanit
2022-02-24 17:18   ` Maxim Levitsky [this message]
2022-03-01 10:47     ` Suravee Suthikulpanit
2022-03-01 11:31       ` Maxim Levitsky
2022-02-21  2:19 ` [RFC PATCH 06/13] KVM: SVM: Add logic to determine x2APIC mode Suravee Suthikulpanit
2022-02-24 17:29   ` Maxim Levitsky
2022-03-03  2:12     ` Suthikulpanit, Suravee
2022-03-03 13:12     ` Suravee Suthikulpanit
2022-02-21  2:19 ` [RFC PATCH 07/13] KVM: SVM: Update avic_kick_target_vcpus to support 32-bit APIC ID Suravee Suthikulpanit
2022-02-24 17:35   ` Maxim Levitsky
2022-03-03 14:41     ` Suravee Suthikulpanit
2022-02-21  2:19 ` [RFC PATCH 08/13] KVM: SVM: Do not update logical APIC ID table when in x2APIC mode Suravee Suthikulpanit
2022-02-24 17:41   ` Maxim Levitsky
2022-03-08  5:24     ` Suthikulpanit, Suravee
2022-02-21  2:19 ` [RFC PATCH 09/13] KVM: SVM: Introduce helper function avic_get_apic_id Suravee Suthikulpanit
2022-02-24 19:46   ` Maxim Levitsky
2022-02-21  2:19 ` [RFC PATCH 10/13] KVM: SVM: Adding support for configuring x2APIC MSRs interception Suravee Suthikulpanit
2022-02-24 19:51   ` Maxim Levitsky
2022-03-07 10:14     ` Suthikulpanit, Suravee
2022-02-21  2:19 ` [RFC PATCH 11/13] KVM: SVM: Add logic to switch between APIC and x2APIC virtualization mode Suravee Suthikulpanit
2022-02-22  5:39   ` Suthikulpanit, Suravee
2022-02-24 20:03   ` Maxim Levitsky
2022-03-04 11:22     ` Suravee Suthikulpanit
2022-03-04 11:51       ` Maxim Levitsky
2022-02-21  2:19 ` [RFC PATCH 12/13] KVM: SVM: Remove APICv inhibit reasone due to x2APIC Suravee Suthikulpanit
2022-02-24 20:06   ` Maxim Levitsky
2022-03-01 14:02     ` Suravee Suthikulpanit
2022-02-21  2:19 ` [RFC PATCH 13/13] KVM: SVM: Use fastpath x2apic IPI emulation when #vmexit with x2AVIC Suravee Suthikulpanit
2022-02-24 20:12   ` Maxim Levitsky
2022-03-07  6:24     ` Suthikulpanit, Suravee
2022-02-22  5:37 ` [RFC PATCH 00/13] Introducing AMD x2APIC Virtualization (x2AVIC) support Suthikulpanit, Suravee

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=9143d9d24d1b169668062a18a5f49bb8cf8e877b.camel@redhat.com \
    --to=mlevitsk@redhat.com \
    --cc=jon.grimm@amd.com \
    --cc=joro@8bytes.org \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=pbonzini@redhat.com \
    --cc=seanjc@google.com \
    --cc=suravee.suthikulpanit@amd.com \
    --cc=terry.bowman@amd.com \
    --cc=wei.huang2@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®