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Hermes SMTP Server) with ESMTPA ID 92480529f98ca63e8f9d6a80b1861c26; Thu, 12 Nov 2026 17:37:41 +0000 (UTC) Message-ID: <915a9103-82e6-4504-8d6e-3d12c4e7af1a@yahoo.com> Date: Thu, 12 Nov 2026 18:37:38 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH net-next v10 07/12] net: dsa: realtek: rtl8365mb: set and get vlan 4k for family D From: Mieczyslaw Nalewaj To: linusw@kernel.org, andrew@lunn.ch, olteanv@gmail.com, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, pabeni@redhat.com, linux@armlinux.org.uk, luizluca@gmail.com, maxime.chevallier@bootlin.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, alvin.sipraga@analog.com, gusfmora@gmail.com, kuncy7@gmail.com, fabianotassotti@gmail.com, gabonpivovich@gmail.com, contact@c127.dev References: Content-Language: pl In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailer: WebService/1.1.26943 mail.backend.jedi.jws.acl:role.jedi.acl.token.atz.jws.hermes.yahoo The hardware structure of 4K VLAN table entries has changed between silicon families. Family D's CVLAN entry is two 16-bit words rather than three: there is no third word extending member/untag past bit 7, and no priority/meter fields at all. The FID field is restricted to a narrower 2-bit width. The chip itself supports both IVL and SVL. IVL_EN (bit 3, versus bit 14 on family C) follows vlan4k->ivl_en. On family D, rtl8365mb_vlan_4k_port_set() enables it while any user port has VLAN filtering enabled (dsa_port_is_vlan_filtering()), so that static and learned FDB/MDB entries use the same key. Family C keeps IVL always enabled, as before. The stored IVL_EN is refreshed on the next port_vlan_add/del for the VID, not on a vlan_filtering change. Reusing the three-word family C layout on family D would read a third word that does not exist as a distinct table word on family D's die. Whatever data happens to be in that register would be folded into member/untag bits [10:8] on read, and written back on every read-modify-write cycle in rtl8365mb_vlan_4k_port_set(). Give family D its own two-word pack/unpack instead: add rtl8365mb_d_vlan_4k_read() and rtl8365mb_d_vlan_4k_write(). The shared code reaches them through the vlan_4k_read and vlan_4k_write pointers in struct rtl8365mb_family_info, so the pack/unpack code needs no is_d() check. The two-word layout matches the vendor switch API for this chip family, which writes only 0x0510/0x0511 for a CVLAN entry. Nothing points to them until the family D info is added together with the chip table entry in the last patch. Until then they are not static and are declared in rtl8365mb_vlan.h, so that the build does not warn about unused functions. Tested-by: Gustavo Foletto Mora Signed-off-by: Mieczyslaw Nalewaj --- drivers/net/dsa/realtek/rtl8365mb_vlan.c | 95 +++++++++++++++++++++++- drivers/net/dsa/realtek/rtl8365mb_vlan.h | 4 + 2 files changed, 97 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.c b/drivers/net/dsa/realtek/rtl8365mb_vlan.c index 566c6bc..bf1a6a9 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_vlan.c +++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.c @@ -53,8 +53,11 @@ #include #include -/* CVLAN (i.e. VLAN4k) table entry layout, u16[3] */ +/* CVLAN (i.e. VLAN4k) table entry layout: u16[3] on family C, u16[2] on + * family D + */ #define RTL8365MB_C_CVLAN_ENTRY_SIZE 3 /* 48-bits */ +#define RTL8365MB_D_CVLAN_ENTRY_SIZE 2 /* 32-bits */ #define RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK GENMASK(7, 0) #define RTL8365MB_CVLAN_MBR_LO_MASK GENMASK(7, 0) #define RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK GENMASK(15, 8) @@ -66,6 +69,9 @@ #define RTL8365MB_CVLAN_ENTRY_D1_METERIDX_MASK GENMASK(13, 9) #define RTL8365MB_CVLAN_METERIDX_LO_MASK GENMASK(4, 0) #define RTL8365MB_CVLAN_ENTRY_D1_IVL_SVL_MASK GENMASK(14, 14) +/* Family D CVLAN entry, word 1 (family D has no word 2) */ +#define RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK GENMASK(3, 3) +#define RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK GENMASK(1, 0) /* extends RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK */ #define RTL8365MB_CVLAN_ENTRY_D2_MBR_EXT_MASK GENMASK(2, 0) #define RTL8365MB_CVLAN_MBR_HI_MASK GENMASK(10, 8) @@ -231,6 +237,45 @@ int rtl8365mb_c_vlan_4k_read(struct realtek_priv *priv, u16 vid, return 0; } +int rtl8365mb_d_vlan_4k_read(struct realtek_priv *priv, u16 vid, + struct rtl8365mb_vlan4k *vlan4k) +{ + u16 data[RTL8365MB_D_CVLAN_ENTRY_SIZE]; + int val; + int ret; + + ret = rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN, + RTL8365MB_TABLE_OP_READ, &vid, 0, 0, + data, RTL8365MB_D_CVLAN_ENTRY_SIZE); + if (ret) + return ret; + + /* Unpack table entry */ + memset(vlan4k, 0, sizeof(*vlan4k)); + vlan4k->vid = vid; + + /* member/untag: d0[7:0]/d0[15:8] on both families. Family C + * extends these into data[2] bits [2:0]/[5:3] for its 9th-11th + * ports; family D's die has only 8 ports and no third table + * word, so data[2] does not exist there and must not be read. + */ + val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, data[0]); + vlan4k->member = FIELD_PREP(RTL8365MB_CVLAN_MBR_LO_MASK, val); + + val = FIELD_GET(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, data[0]); + vlan4k->untag = FIELD_PREP(RTL8365MB_CVLAN_UNTAG_LO_MASK, val); + + vlan4k->fid = FIELD_GET(RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK, + data[1]); + /* Family D has no priority/meter fields in this entry - + * left zeroed by the memset() above. + */ + vlan4k->ivl_en = FIELD_GET(RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK, + data[1]); + + return 0; +} + int rtl8365mb_c_vlan_4k_write(struct realtek_priv *priv, const struct rtl8365mb_vlan4k *vlan4k) { @@ -277,6 +322,38 @@ int rtl8365mb_c_vlan_4k_write(struct realtek_priv *priv, data, ARRAY_SIZE(data)); } +int rtl8365mb_d_vlan_4k_write(struct realtek_priv *priv, + const struct rtl8365mb_vlan4k *vlan4k) +{ + /* Unknown bits of word 1 are written as zero, same as the vendor + * API does for this chip family. + */ + u16 data[RTL8365MB_D_CVLAN_ENTRY_SIZE] = { 0 }; + u16 vid; + int val; + + /* Pack table entry value */ + val = FIELD_GET(RTL8365MB_CVLAN_MBR_LO_MASK, vlan4k->member); + data[0] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D0_MBR_MASK, val); + + val = FIELD_GET(RTL8365MB_CVLAN_UNTAG_LO_MASK, vlan4k->untag); + data[0] |= FIELD_PREP(RTL8365MB_CVLAN_ENTRY_D0_UNTAG_MASK, val); + + data[1] |= FIELD_PREP(RTL8365MB_D_CVLAN_ENTRY_D1_IVL_EN_MASK, + vlan4k->ivl_en); + data[1] |= FIELD_PREP(RTL8365MB_D_CVLAN_ENTRY_D1_FID_MASK, + vlan4k->fid); + /* No priority/meter/member-untag-extension fields exist in + * family D's 2-word entry - data[1] and data[0] above are + * the whole entry, and data[2] is not part of it at all. + */ + + vid = vlan4k->vid; + return rtl8365mb_table_query(priv, RTL8365MB_TABLE_CVLAN, + RTL8365MB_TABLE_OP_WRITE, &vid, 0, 0, + data, RTL8365MB_D_CVLAN_ENTRY_SIZE); +} + static int rtl8365mb_vlan_4k_port_set(struct dsa_switch *ds, int port, const struct switchdev_obj_port_vlan *vlan, @@ -314,7 +391,21 @@ rtl8365mb_vlan_4k_port_set(struct dsa_switch *ds, int port, vlan4k.untag |= BIT(port); else vlan4k.untag &= ~BIT(port); - vlan4k.ivl_en = true; /* always use Independent VLAN Learning */ + + /* Family C always uses IVL. On family D, IVL is on while any user + * port has VLAN filtering enabled, so that static entries match + * learned ones in a VLAN-unaware bridge (SVL). + */ + if (!rtl8365mb_is_d(priv)) { + vlan4k.ivl_en = true; + } else { + struct dsa_port *dp; + + vlan4k.ivl_en = false; + dsa_switch_for_each_user_port(dp, ds) + if (dsa_port_is_vlan_filtering(dp)) + vlan4k.ivl_en = true; + } ret = fi->vlan_4k_write(priv, &vlan4k); if (ret) { diff --git a/drivers/net/dsa/realtek/rtl8365mb_vlan.h b/drivers/net/dsa/realtek/rtl8365mb_vlan.h index 009b127..012c07d 100644 --- a/drivers/net/dsa/realtek/rtl8365mb_vlan.h +++ b/drivers/net/dsa/realtek/rtl8365mb_vlan.h @@ -24,6 +24,10 @@ int rtl8365mb_c_vlan_4k_read(struct realtek_priv *priv, u16 vid, struct rtl8365mb_vlan4k *vlan4k); int rtl8365mb_c_vlan_4k_write(struct realtek_priv *priv, const struct rtl8365mb_vlan4k *vlan4k); +int rtl8365mb_d_vlan_4k_read(struct realtek_priv *priv, u16 vid, + struct rtl8365mb_vlan4k *vlan4k); +int rtl8365mb_d_vlan_4k_write(struct realtek_priv *priv, + const struct rtl8365mb_vlan4k *vlan4k); int rtl8365mb_vlan_port_get_pvid(struct realtek_priv *priv, int port, u16 *pvid); -- 2.53.0