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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-658b46ac0e8sm2677629a12.34.2026.01.29.03.19.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jan 2026 03:19:08 -0800 (PST) Message-ID: <91812db8-9774-468e-8a8b-10699a63310c@oss.qualcomm.com> Date: Thu, 29 Jan 2026 12:19:06 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: sm6350: add LPASS LPI pin controller To: Luca Weiss , Dmitry Baryshkov Cc: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> <20260128-sm6350-lpi-tlmm-v1-4-36583f2a2a2a@fairphone.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Z93h3XRA c=1 sm=1 tr=0 ts=697b422e cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=6H0WHjuAAAAA:8 a=8gWlQ0A84ExjddM39AAA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-ORIG-GUID: cAPlriIoPe6mKax-De6Too5uPj4mjAHV X-Proofpoint-GUID: cAPlriIoPe6mKax-De6Too5uPj4mjAHV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI5MDA3NiBTYWx0ZWRfX1mk1LJAM/6tN dk69zwfk5mln8ZKwasqFzRMp8oFjNGxanZKAIP5RrJhHUdukfkHVMOyxgAsbPaQHuOw6rpnZBcn F62rfCMo2Jv9xlHqffgf5Ez4Lu+zzmaD3qDqSaDbiSQuXFCcojt52FdfgJykQvMUtMKZejtegpa FpHMQNn+eA3WPcBxsm+cB/zHAniFg7BEQTXUXaPSmEUjmxRGuDHb7l2SG7DoCOVEMGgzNE3Eu5T BI0UFeYkMMRtjpJUMzlUler7y1tWM8PJ8B6roixghAfrPCaUde6MAzJI2d+vCKfshDgH60hjHUp hkgUkXeoABfCoHaB0JJjqLZjK2wo1N52/a7FDp6XXDV0w14T0PawWcJWm+6CWx7NQgOn4VTcpdA 3PoGn3JXa+vPdqT2a9jn4gwMMH+cNLxqNtfqKXD2QgKz12wwYSiD3h37seEugODhwLO5LSWy5tE HDSO2zUVceHBPlAjeNg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-29_02,2026-01-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 clxscore=1015 phishscore=0 spamscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601290076 On 1/29/26 9:32 AM, Luca Weiss wrote: > On Wed Jan 28, 2026 at 11:16 PM CET, Dmitry Baryshkov wrote: >> On Wed, Jan 28, 2026 at 01:26:52PM +0100, Luca Weiss wrote: >>> Add LPASS LPI pinctrl node required for audio functionality on SM6350. >>> >>> Signed-off-by: Luca Weiss >>> --- >>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 66 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> index 9f9b9f9af0da..b1fb6c812da7 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> @@ -1448,6 +1448,72 @@ compute-cb@5 { >>> }; >>> }; >>> >>> + lpass_tlmm: pinctrl@33c0000 { >>> + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; >>> + reg = <0x0 0x033c0000 0x0 0x20000>, >>> + <0x0 0x03550000 0x0 0x10000>; >>> + gpio-controller; >>> + #gpio-cells = <2>; >>> + gpio-ranges = <&lpass_tlmm 0 0 15>; >>> + >>> + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, >>> + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; >>> + clock-names = "core", >>> + "audio"; >>> + >>> + i2s1_active: i2s1-active-state { >>> + clk-pins { >>> + pins = "gpio6"; >>> + function = "i2s1_clk"; >>> + drive-strength = <8>; >>> + bias-disable; >>> + output-high; >> >> This looks suspicious for the clock pin. >> >>> + }; >>> + >>> + ws-pins { >>> + pins = "gpio7"; >>> + function = "i2s1_ws"; >>> + drive-strength = <8>; >>> + bias-disable; >>> + output-high; >> >> The same >> >>> + }; >>> + >>> + data-pins { >>> + pins = "gpio8", "gpio9"; >>> + function = "i2s1_data"; >>> + drive-strength = <8>; >>> + bias-disable; >>> + output-high; >> >> And here. > > I've taken this pinctrl from downstream lagoon-lpi.dtsi. There the > active config for these pins have "output-high;" set. > > And fwiw this pinctrl works fine at runtime for driving the speaker. I tried to find an answer. A doc for this SoC says that i2s clock pins should be at output-low (2 mA) when muxed to the i2s_xxx function, with no information about bias settings (perhaps bias-disable), and in sleep they should be the same (minus the drive strength note, but 2mA is the lowest setting) I am further confused because the output-enable bit in the cfg register specifically says "when in GPIO mode" Konrad