From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S944859AbdEZUOl convert rfc822-to-8bit (ORCPT ); Fri, 26 May 2017 16:14:41 -0400 Received: from terminus.zytor.com ([65.50.211.136]:35055 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934404AbdEZUOd (ORCPT ); Fri, 26 May 2017 16:14:33 -0400 Date: Fri, 26 May 2017 12:40:17 -0700 User-Agent: K-9 Mail for Android In-Reply-To: <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> References: <20170525203334.867-1-kirill.shutemov@linux.intel.com> <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging To: "Kirill A. Shutemov" , Linus Torvalds CC: "Kirill A. Shutemov" , Andrew Morton , the arch/x86 maintainers , Thomas Gleixner , Ingo Molnar , Andi Kleen , Dave Hansen , Andy Lutomirski , "linux-arch@vger.kernel.org" , linux-mm , Linux Kernel Mailing List From: hpa@zytor.com Message-ID: <91E86DF1-9814-444B-AD43-706246D768EC@zytor.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On May 26, 2017 6:00:57 AM PDT, "Kirill A. Shutemov" wrote: >On Thu, May 25, 2017 at 04:24:24PM -0700, Linus Torvalds wrote: >> On Thu, May 25, 2017 at 1:33 PM, Kirill A. Shutemov >> wrote: >> > Here' my first attempt to bring boot-time between 4- and 5-level >paging. >> > It looks not too terrible to me. I've expected it to be worse. >> >> If I read this right, you just made it a global on/off thing. >> >> May I suggest possibly a different model entirely? Can you make it a >> per-mm flag instead? >> >> And then we >> >> (a) make all kthreads use the 4-level page tables >> >> (b) which means that all the init code uses the 4-level page tables >> >> (c) which means that all those checks for "start_secondary" etc can >> just go away, because those all run with 4-level page tables. >> >> Or is it just much too expensive to switch between 4-level and >5-level >> paging at run-time? > >Hm.. > >I don't see how kernel threads can use 4-level paging. It doesn't work >from virtual memory layout POV. Kernel claims half of full virtual >address >space for itself -- 256 PGD entries, not one as we would effectively >have >in case of switching to 4-level paging. For instance, addresses, where >vmalloc and vmemmap are mapped, are not canonical with 4-level paging. > >And you cannot see whole direct mapping of physical memory. Back to >highmem? (Please, no, please). > >We could possible reduce number of PGD required by kernel. Currently, >layout for 5-level paging allows up-to 55-bit physical memory. It's >redundant as SDM claim that we never will get more than 52. So we could >reduce size of kernel part of layout by few bits, but not definitely to >1. > >I don't see how it can possibly work. > >Besides difficulties of getting switching between paging modes correct, >that Andy mentioned, it will also hurt performance. You cannot switch >between paging modes directly. It would require disabling paging >completely. It means we loose benefit from global page table entries on >such switching. More page-walks. > >Even ignoring all of above, I don't see much benefit of having per-mm >switching. It adds complexity without much benefit -- saving few lines >of >logic during early boot doesn't look as huge win to me. It also makes no sense – the kernel threads only need one common page table anyway. -- Sent from my Android device with K-9 Mail. Please excuse my brevity.