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Date: Tue, 12 Nov 2013 10:06:05 -0800
From: =?utf-8?B?U8O2cmVu?= Brinkmann <soren.brinkmann@xilinx.com>
To: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>,
        Peter Crosthwaite <peter.crosthwaite@xilinx.com>
CC: "rob.herring@calxeda.com" <rob.herring@calxeda.com>,
        Pawel Moll <Pawel.Moll@arm.com>, Mark Rutland <Mark.Rutland@arm.com>,
        Stephen Warren <swarren@wwwdotorg.org>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
        Russell King <linux@arm.linux.org.uk>,
        Michal Simek <michal.simek@xilinx.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
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Subject: Re: [PATCH 2/7] arm: dt: zynq: Add 'cpus' node
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On Mon, Nov 11, 2013 at 06:57:44PM +0000, Sudeep KarkadaNagesha wrote:
> On 08/11/13 21:21, Soren Brinkmann wrote:
> > Add a 'cpus' node to describe the CPU cores of Zynq.
> > 
> > Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
> > Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> > ---
> >  arch/arm/boot/dts/zynq-7000.dtsi | 27 +++++++++++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> > index 27ebc1ba9671..37fc04525142 100644
> > --- a/arch/arm/boot/dts/zynq-7000.dtsi
> > +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> > @@ -15,6 +15,33 @@
> >  / {
> >  	compatible = "xlnx,zynq-7000";
> >  
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu@0 {
> > +			compatible = "arm,cortex-a9";
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +			clocks = <&clkc 3>;
> > +			i-cache-size = <0x8000>;
> > +			i-cache-line-size = <0x20>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <0x20>;
> 
> These cache properties can be identified through CCSIDR(Cache Size ID Registers)
> on ARMv7 Cortex implementations. It's better not to have these in DT if they can
> be identified runtime.
Sounds good to me. I'll go ahead an remove them.

	Thanks,
	Sören