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Wed, 18 Dec 2019 06:30:36 -0800 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id xBIEUVRN021544; Wed, 18 Dec 2019 06:30:31 -0800 Received: from [172.30.17.107] by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1ihaLO-0007XX-Sm; Wed, 18 Dec 2019 06:30:31 -0800 Subject: Re: [PATCH v2] ARM: dts: zynq: enablement of coresight topology To: Michal Simek , linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com Cc: Zumeng Chen , Quanyang Wang , Mathieu Poirier , devicetree@vger.kernel.org, Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org References: <882627bc1ecd622355fb72b742b4e3c013d0b1ca.1576161496.git.michal.simek@xilinx.com> From: Michal Simek Message-ID: <91cd571f-6c41-55bd-87d8-8925dc0a0ae4@xilinx.com> Date: Wed, 18 Dec 2019 15:30:28 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <882627bc1ecd622355fb72b742b4e3c013d0b1ca.1576161496.git.michal.simek@xilinx.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(189003)(199004)(186003)(5660300002)(26005)(8936002)(4326008)(36756003)(2906002)(31696002)(2616005)(498600001)(81156014)(8676002)(81166006)(426003)(9786002)(6636002)(70586007)(70206006)(336012)(54906003)(31686004)(44832011)(356004)(6666004);DIR:OUT;SFP:1101;SCL:1;SRVR:BN7PR02MB4082;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f34ca03c-523c-48b2-fac5-08d783c6dcd0 X-MS-TrafficTypeDiagnostic: BN7PR02MB4082: X-LD-Processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-Forefront-PRVS: 0255DF69B9 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OdC4tgkJtXeC5u4Jt4ymfkvd8xrk0buPwS1zNKSHHSTofN74OL42FdyPeWrPaPLswYs8zLRrwPY6zuGw6ie2ymoBgtjhac1nMKZFEPqL0s48ftbEwbkmfXbDtaPMNy189MumGwCYn2nLJJQihGCBPmQqRO/0tKMkE34Gpcjrc9P9kHMsQeQHmEedHpycrAMi0CtBFT+jy1lx5u7+1XV32p7LVnSu/xHZ/DphHGKFeQHFOYSX1wPo9PkRcIF+djTG1HAXS32DO+jdSCjjl0kt0f5vJXYrTO8GKcSBexHvnI82WWNJTxfLjOhXMEVrLqVabk1CtO5UU827ry+OscA6jTm6K68YdWYBLj/F/C/lrcFxsiPKuk3LCb9NozZZlmqTndG237MnD3frz55Wd7MlXk2cMexQE506a7PPtalJCkSZEF54ZiHEYK/404bK8UuW X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2019 14:30:42.5469 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f34ca03c-523c-48b2-fac5-08d783c6dcd0 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR02MB4082 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12. 12. 19 15:38, Michal Simek wrote: > From: Zumeng Chen > > This patch is to build the coresight topology structure of zynq-7000 > series according to the docs of coresight and userguide of zynq-7000. > > Signed-off-by: Zumeng Chen > Signed-off-by: Quanyang Wang > Reviewed-by: Mathieu Poirier > Signed-off-by: Michal Simek > --- > > Changes in v2: > - Remove slava-mode from replicator in-ports > - Remove ITM completely > > arch/arm/boot/dts/zynq-7000.dtsi | 135 +++++++++++++++++++++++++++++++ > 1 file changed, 135 insertions(+) > > diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi > index ca6425ad794c..db3899b07992 100644 > --- a/arch/arm/boot/dts/zynq-7000.dtsi > +++ b/arch/arm/boot/dts/zynq-7000.dtsi > @@ -59,6 +59,39 @@ regulator_vccpint: fixedregulator { > regulator-always-on; > }; > > + replicator { > + compatible = "arm,coresight-static-replicator"; > + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; > + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; > + > + out-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* replicator output ports */ > + port@0 { > + reg = <0>; > + replicator_out_port0: endpoint { > + remote-endpoint = <&tpiu_in_port>; > + }; > + }; > + port@1 { > + reg = <1>; > + replicator_out_port1: endpoint { > + remote-endpoint = <&etb_in_port>; > + }; > + }; > + }; > + in-ports { > + /* replicator input port */ > + port { > + replicator_in_port0: endpoint { > + remote-endpoint = <&funnel_out_port>; > + }; > + }; > + }; > + }; > + > amba: amba { > compatible = "simple-bus"; > #address-cells = <1>; > @@ -365,5 +398,107 @@ watchdog0: watchdog@f8005000 { > reg = <0xf8005000 0x1000>; > timeout-sec = <10>; > }; > + > + etb@f8801000 { > + compatible = "arm,coresight-etb10", "arm,primecell"; > + reg = <0xf8801000 0x1000>; > + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; > + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; > + in-ports { > + port { > + etb_in_port: endpoint { > + remote-endpoint = <&replicator_out_port1>; > + }; > + }; > + }; > + }; > + > + tpiu@f8803000 { > + compatible = "arm,coresight-tpiu", "arm,primecell"; > + reg = <0xf8803000 0x1000>; > + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; > + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; > + in-ports { > + port { > + tpiu_in_port: endpoint { > + remote-endpoint = <&replicator_out_port0>; > + }; > + }; > + }; > + }; > + > + funnel@f8804000 { > + compatible = "arm,coresight-static-funnel", "arm,primecell"; > + reg = <0xf8804000 0x1000>; > + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; > + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; > + > + /* funnel output ports */ > + out-ports { > + port { > + funnel_out_port: endpoint { > + remote-endpoint = > + <&replicator_in_port0>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* funnel input ports */ > + port@0 { > + reg = <0>; > + funnel0_in_port0: endpoint { > + remote-endpoint = <&ptm0_out_port>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + funnel0_in_port1: endpoint { > + remote-endpoint = <&ptm1_out_port>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + funnel0_in_port2: endpoint { > + }; > + }; > + /* The other input ports are not connect to anything */ > + }; > + }; > + > + ptm@f889c000 { > + compatible = "arm,coresight-etm3x", "arm,primecell"; > + reg = <0xf889c000 0x1000>; > + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; > + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; > + cpu = <&cpu0>; > + out-ports { > + port { > + ptm0_out_port: endpoint { > + remote-endpoint = <&funnel0_in_port0>; > + }; > + }; > + }; > + }; > + > + ptm@f889d000 { > + compatible = "arm,coresight-etm3x", "arm,primecell"; > + reg = <0xf889d000 0x1000>; > + clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; > + clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; > + cpu = <&cpu1>; > + out-ports { > + port { > + ptm1_out_port: endpoint { > + remote-endpoint = <&funnel0_in_port1>; > + }; > + }; > + }; > + }; > }; > }; > Applied to zynq/dt. Thanks, Michal