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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbefc655csm986203666b.19.2026.02.03.01.21.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Feb 2026 01:21:37 -0800 (PST) Message-ID: <91e91f5e-93af-466b-92f7-b2e88dc8d73f@oss.qualcomm.com> Date: Tue, 3 Feb 2026 10:21:36 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 To: Sushrut Shree Trivedi , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260203-industrial-mezzanine-pcie-v2-0-8579ed6bf931@oss.qualcomm.com> <20260203-industrial-mezzanine-pcie-v2-2-8579ed6bf931@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260203-industrial-mezzanine-pcie-v2-2-8579ed6bf931@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAzMDA3MyBTYWx0ZWRfX/uGS3Ez27wZb hmiECeuO5E419BxMu2iyX89To10Gui1fxsTJ/sZIjbulyB2ts+XxtqJpiaCLWe3jvVkK9sgRLdF AyJfSJhpH0atRe4uKN+lc8eH+l2/CxILwK4St22bobg4p1lRh6rXn7RU+YWbAZEYA40cTowPfEs U6W8MvejOnjTSnSIdmOOT9va07edCD+oyib08LGtYXg4xkYwF1u/SOtszdcKlzd228mgYpXPcKG i13//l1tHNYFW9PH8W5UfJxejJG+rMS0RB8GE4oBS86kY5DcP3P7Z8LM7HcPGVYIYzyReOxz5qx 1bVghlQFSPOq1vSzCHuKQAInTa1kbq/xvcfqPVB0fQ3BKd8bVCtyuoRQXnkRw9YUyL7TXkkx5H0 3UMgPq1ZG7OKwitZyfAhOUJAuJlDcsvSMdIYc4UIWUv+Ha5EKY8iWBmCsQ3hR9B1wuI2EsGvcpD R4HPf3L7e6eARjVQ+8g== X-Proofpoint-ORIG-GUID: VzX1a0FRz69W0JMOVGvkzyy1acrr65eI X-Authority-Analysis: v=2.4 cv=L4sQguT8 c=1 sm=1 tr=0 ts=6981be23 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=9kIy5wuRr3uUqB62-wcA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: VzX1a0FRz69W0JMOVGvkzyy1acrr65eI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-03_02,2026-02-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 malwarescore=0 spamscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602030073 On 2/3/26 5:31 AM, Sushrut Shree Trivedi wrote: > Add a node for the second TC9563 PCIe switch on PCIe1, which is connected > in cascade to the first TC9563 switch via the former's downstream port. > > Two embedded Ethernet devices are present on one of the downstream > ports of this second switch as well. All the ports present in the > node represent the downstream ports and embedded endpoints. > > The second TC9563 is powered up via the same LDO regulators as the first > one, and these can be controlled via two GPIOs, which are already present > as fixed regulators. This TC9563 can also be configured through I2C. > > Signed-off-by: Sushrut Shree Trivedi > --- > .../qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 96 ++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 12 +-- > 2 files changed, 102 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > index 89bbcab0908d..1744c9c8bd50 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > @@ -146,6 +146,91 @@ pcie0_switch0_eth1: pci@0,1 { > }; > }; > > +&pcie1 { > + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, > + <0x100 &apps_smmu 0x1c81 0x1>, Please set your tab width to 8 and align the '<'s [...] > +&pcie1_switch0_dsp1 { > + pcie1_switch1_usp: pcie@0,0 { This label is unused [...] > + pcie1_switch1_dsp1: pcie@1,0 { > + reg = <0x40800 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + }; > + > + pcie1_switch1_dsp2: pcie@2,0 { > + reg = <0x41000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + }; > + > + pcie1_switch1_dsp3: pcie@3,0 { And so are all three of these > + reg = <0x41800 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + > + pcie1_switch1_eth0: pci@0,0 { > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + }; > + > + pcie1_switch1_eth1: pci@0,1 { These two are unused as well [...] > + pcie1_switch0_dsp1: pcie@1,0 { This one is in use > reg = <0x20800 0x0 0x0 0x0 0x0>; > #address-cells = <3>; > #size-cells = <2>; > @@ -862,7 +862,7 @@ pcie@1,0 { > bus-range = <0x3 0xff>; > }; > > - pcie@2,0 { > + pcie1_switch0_dsp2: pcie@2,0 { > reg = <0x21000 0x0 0x0 0x0 0x0>; > #address-cells = <3>; > #size-cells = <2>; > @@ -872,7 +872,7 @@ pcie@2,0 { > bus-range = <0x4 0xff>; > }; > > - pcie@3,0 { > + pcie1_switch0_dsp3: pcie@3,0 { But these two aren't. Plus the DSP3 seems to be hardwired to eth so it seems like that won't ever change. DSP2 will understandably be useful, since any derivative of this mezz could attach more devices > reg = <0x21800 0x0 0x0 0x0 0x0>; > #address-cells = <3>; > #size-cells = <2>; > @@ -880,7 +880,7 @@ pcie@3,0 { > ranges; > bus-range = <0x5 0xff>; > > - pci@0,0 { > + pcie1_switch0_eth0: pci@0,0 { > reg = <0x50000 0x0 0x0 0x0 0x0>; > #address-cells = <3>; > #size-cells = <2>; > @@ -888,7 +888,7 @@ pci@0,0 { > ranges; > }; > > - pci@0,1 { > + pcie1_switch0_eth1: pci@0,1 { These two are again unused Konrad