Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

[Kefeng Wang <wangkefeng.wang@huawei.com>]

On 2021/9/17 22:14, Jisheng Zhang wrote:
> On Thu, 16 Sep 2021 13:08:53 +0000
> Chen Huang <chenhuang5@huawei.com> wrote:
>
>> The patchset improves RISCV unaligned memory accesses, selects
>> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
>> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
>> of unaligned memory accesses.
>>
>> If CPU don't support unaligned memory accesses for now, please
>> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
>> don't support unaligned memory accesses, I don't choose the
>> CONFIG for them.
> This will break unified kernel Image for riscv. Obviously, we will have
> two images for efficient unaligned access platforms and non-efficient
> unaligned access platforms. IMHO, we may need alternative mechanism or
> something else to dynamically enable related code path.

it won't break unified kernel Image for riscv, if one SoC choose

CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory

accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has

similar configuration.

Yes,  it could be an optimization via alternative mechanism or something 
else to

dynamically enable related code path later.

>
> Regards
>
>> Changes since v1:
>>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
>>     unaligned memory accesses, add an option for CPUs to choose it or not.
>>
>> Chen Huang (2):
>>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
>>    riscv: Support DCACHE_WORD_ACCESS
>>
>>   arch/riscv/Kconfig                      |  5 ++++
>>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
>>   2 files changed, 42 insertions(+)
>>
>
> .
>