Re: [PATCH v2 3/3] pwm: axi-pwmgen: fix missing separate external clock

["Nuno Sá" <noname.nuno@gmail.com>]

On Thu, 2025-05-22 at 09:49 -0500, David Lechner wrote:
> Add proper support for external clock to the AXI PWM generator driver.
> 
> In most cases, the HDL for this IP block is compiled with the default
> ASYNC_CLK_EN=1. With this option, there is a separate external clock
> that drives the PWM output separate from the peripheral clock. So the
> driver should be enabling the "axi" clock to power the peripheral and
> the "ext" clock to drive the PWM output.
> 
> When ASYNC_CLK_EN=0, the "axi" clock is also used to drive the PWM
> output and there is no "ext" clock.
> 
> Previously, if there was a separate external clock, users had to specify
> only the external clock and (incorrectly) omit the AXI clock in order
> to get the correct operating frequency for the PWM output.
> 
> The devicetree bindings are updated to fix this shortcoming and this
> patch changes the driver to match the new bindings. To preserve
> compatibility with any existing dtbs that specify only one clock, we
> don't require the clock name on the first clock.
> 
> Fixes: 41814fe5c782 ("pwm: Add driver for AXI PWM generator")
> Signed-off-by: David Lechner <dlechner@baylibre.com>
> ---

Acked-by: Nuno Sá <nuno.sa@analog.com>

>  drivers/pwm/pwm-axi-pwmgen.c | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
> index
> 4337c8f5acf055fc87dc134f2a70b99b0cb5ede6..60dcd354237316bced2d951b7f0b116c8291
> bb0d 100644
> --- a/drivers/pwm/pwm-axi-pwmgen.c
> +++ b/drivers/pwm/pwm-axi-pwmgen.c
> @@ -257,7 +257,7 @@ static int axi_pwmgen_probe(struct platform_device *pdev)
>  	struct regmap *regmap;
>  	struct pwm_chip *chip;
>  	struct axi_pwmgen_ddata *ddata;
> -	struct clk *clk;
> +	struct clk *axi_clk, *clk;
>  	void __iomem *io_base;
>  	int ret;
>  
> @@ -280,9 +280,26 @@ static int axi_pwmgen_probe(struct platform_device *pdev)
>  	ddata = pwmchip_get_drvdata(chip);
>  	ddata->regmap = regmap;
>  
> -	clk = devm_clk_get_enabled(dev, NULL);
> +	/*
> +	 * Using NULL here instead of "axi" for backwards compatibility.
> There
> +	 * are some dtbs that don't give clock-names and have the "ext" clock
> +	 * as the one and only clock (due to mistake in the original
> bindings).
> +	 */
> +	axi_clk = devm_clk_get_enabled(dev, NULL);
> +	if (IS_ERR(axi_clk))
> +		return dev_err_probe(dev, PTR_ERR(axi_clk), "failed to get
> axi clock\n");
> +
> +	clk = devm_clk_get_optional_enabled(dev, "ext");
>  	if (IS_ERR(clk))
> -		return dev_err_probe(dev, PTR_ERR(clk), "failed to get
> clock\n");
> +		return dev_err_probe(dev, PTR_ERR(clk), "failed to get ext
> clock\n");
> +
> +	/*
> +	 * If there is no "ext" clock, it means the HDL was compiled with
> +	 * ASYNC_CLK_EN=0. In this case, the AXI clock is also used for the
> +	 * PWM output clock.
> +	 */
> +	if (!clk)
> +		clk = axi_clk;
>  
>  	ret = devm_clk_rate_exclusive_get(dev, clk);
>  	if (ret)