From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C2242512CD for ; Tue, 25 Feb 2025 06:08:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740463732; cv=none; b=MRPf8gnIUGHQU49QA4OxFFlRTlhu6j/ehs834zQ7QfqhpTHPd066o2Zjo48WqLWaX2N4TUbnZvHuR3jUm8ZlOc9RSL/N7oc3DcAFIwMhSe+H7DTYF3Q2Dmq0Fs/8R0GIFg7dg6Y7YcJepDs8uXGYU6lHmcIzrEfIcMZW92daZGU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740463732; c=relaxed/simple; bh=QRwPOIkwUosvoITQm+whjqnlHGYKUY+PhOqgRUa1iEg=; h=Subject:To:CC:References:From:Message-ID:Date:MIME-Version: In-Reply-To:Content-Type; b=Jo87sJURbLLlYGfhrvYjOUz4R3wExLu5wNXCWxnz4XrB53F/qG7oUH/Fv9EF/ZKrWkhrNwmS5wJcSuc4wAtCJ3A0HlUC71Bu0uU20oTeRykv0nyIHQEZZArBserxD5zjtWbWEwapM6gCkU4K/0j0V34nLSYw9ffv2WbYrO7RZvQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.44]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Z26Xl21DTz21nvV; Tue, 25 Feb 2025 14:05:43 +0800 (CST) Received: from dggpemf500002.china.huawei.com (unknown [7.185.36.57]) by mail.maildlp.com (Postfix) with ESMTPS id 5F8381402CA; Tue, 25 Feb 2025 14:08:47 +0800 (CST) Received: from [10.174.178.247] (10.174.178.247) by dggpemf500002.china.huawei.com (7.185.36.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 25 Feb 2025 14:08:46 +0800 Subject: Re: [PATCH v11 3/4] arm64: topology: Support SMT control on ACPI based system To: Yicong Yang , , , , , , , , , , , , CC: , , , , , , , , , , , , References: <20250218141018.18082-1-yangyicong@huawei.com> <20250218141018.18082-4-yangyicong@huawei.com> From: Hanjun Guo Message-ID: <92193a09-271e-895e-f77f-d3952bdfdf49@huawei.com> Date: Tue, 25 Feb 2025 14:08:45 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In-Reply-To: <20250218141018.18082-4-yangyicong@huawei.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpemf500002.china.huawei.com (7.185.36.57) On 2025/2/18 22:10, Yicong Yang wrote: > From: Yicong Yang > > For ACPI we'll build the topology from PPTT and we cannot directly > get the SMT number of each core. Instead using a temporary xarray > to record the heterogeneous information (from ACPI_PPTT_ACPI_IDENTICAL) > and SMT information of the first core in its heterogeneous CPU cluster > when building the topology. Then we can know the largest SMT number > in the system. If a homogeneous system's using ACPI 6.2 or later, > all the CPUs should be under the root node of PPTT. There'll be > only one entry in the xarray and all the CPUs in the system will > be assumed identical. > > The core's SMT control provides two interface to the users [1]: > 1) enable/disable SMT by writing on/off > 2) enable/disable SMT by writing thread number 1/max_thread_number > > If a system have more than one SMT thread number the 2) may > not handle it well, since there're multiple thread numbers in the > system and 2) only accept 1/max_thread_number. So issue a warning > to notify the users if such system detected. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/ABI/testing/sysfs-devices-system-cpu#n542 > > Reviewed-by: Jonathan Cameron > Signed-off-by: Yicong Yang > --- > arch/arm64/kernel/topology.c | 66 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c > index 1a2c72f3e7f8..6eba1ac091ee 100644 > --- a/arch/arm64/kernel/topology.c > +++ b/arch/arm64/kernel/topology.c > @@ -15,8 +15,10 @@ > #include > #include > #include > +#include > #include > #include > +#include > > #include > #include > @@ -37,17 +39,28 @@ static bool __init acpi_cpu_is_threaded(int cpu) > return !!is_threaded; > } > > +struct cpu_smt_info { > + unsigned int thread_num; > + int core_id; > +}; > + > /* > * Propagate the topology information of the processor_topology_node tree to the > * cpu_topology array. > */ > int __init parse_acpi_topology(void) > { > + unsigned int max_smt_thread_num = 0; > + struct cpu_smt_info *entry; > + struct xarray hetero_cpu; > + unsigned long hetero_id; > int cpu, topology_id; > > if (acpi_disabled) > return 0; > > + xa_init(&hetero_cpu); > + > for_each_possible_cpu(cpu) { > topology_id = find_acpi_cpu_topology(cpu, 0); > if (topology_id < 0) > @@ -57,6 +70,34 @@ int __init parse_acpi_topology(void) > cpu_topology[cpu].thread_id = topology_id; > topology_id = find_acpi_cpu_topology(cpu, 1); > cpu_topology[cpu].core_id = topology_id; > + > + /* > + * In the PPTT, CPUs below a node with the 'identical > + * implementation' flag have the same number of threads. > + * Count the number of threads for only one CPU (i.e. > + * one core_id) among those with the same hetero_id. > + * See the comment of find_acpi_cpu_topology_hetero_id() > + * for more details. > + * > + * One entry is created for each node having: > + * - the 'identical implementation' flag > + * - its parent not having the flag > + */ > + hetero_id = find_acpi_cpu_topology_hetero_id(cpu); > + entry = xa_load(&hetero_cpu, hetero_id); > + if (!entry) { > + entry = kzalloc(sizeof(*entry), GFP_KERNEL); > + WARN_ON_ONCE(!entry); > + > + if (entry) { > + entry->core_id = topology_id; > + entry->thread_num = 1; > + xa_store(&hetero_cpu, hetero_id, > + entry, GFP_KERNEL); > + } > + } else if (entry->core_id == topology_id) { > + entry->thread_num++; > + } > } else { > cpu_topology[cpu].thread_id = -1; > cpu_topology[cpu].core_id = topology_id; > @@ -67,6 +108,31 @@ int __init parse_acpi_topology(void) > cpu_topology[cpu].package_id = topology_id; > } > > + /* > + * This should be a short loop depending on the number of heterogeneous > + * CPU clusters. Typically on a homogeneous system there's only one > + * entry in the XArray. > + */ > + xa_for_each(&hetero_cpu, hetero_id, entry) { > + if (entry->thread_num != max_smt_thread_num && max_smt_thread_num) > + pr_warn_once("Heterogeneous SMT topology is partly supported by SMT control\n"); > + > + max_smt_thread_num = max(max_smt_thread_num, entry->thread_num); > + xa_erase(&hetero_cpu, hetero_id); > + kfree(entry); > + } > + > + /* > + * Notify the CPU framework of the SMT support. Initialize the > + * max_smt_thread_num to 1 if no SMT support detected. A thread > + * number of 1 can be handled by the framework so we don't need > + * to check max_smt_thread_num to see we support SMT or not. > + */ > + if (!max_smt_thread_num) > + max_smt_thread_num = 1; > + > + cpu_smt_set_num_threads(max_smt_thread_num, max_smt_thread_num); > + xa_destroy(&hetero_cpu); > return 0; > } > #endif Looks good to me, Reviewed-by: Hanjun Guo Thanks Hanjun