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([2a02:908:8b3:1840:9c00:9bd:fed3:8356]) by smtp.gmail.com with ESMTPSA id k8-20020a1709061c0800b0099d9b50d786sm720356ejg.199.2023.08.12.17.23.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 12 Aug 2023 17:23:23 -0700 (PDT) Message-ID: <92396880-edb5-d8e0-4fcf-54aeaa2b40d7@gmail.com> Date: Sun, 13 Aug 2023 02:23:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 02/11] drm/bridge: tc358768: Fix bit updates Content-Language: en-US To: Tomi Valkeinen , =?UTF-8?Q?P=c3=a9ter_Ujfalusi?= , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Francesco Dolcini Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Aradhya Bhatia References: <20230804-tc358768-v1-0-1afd44b7826b@ideasonboard.com> <20230804-tc358768-v1-2-1afd44b7826b@ideasonboard.com> <241937b4-1ef8-abad-7c4a-b26bfab86a3a@ideasonboard.com> From: Maxim Schwalm In-Reply-To: <241937b4-1ef8-abad-7c4a-b26bfab86a3a@ideasonboard.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 11.08.23 19:02, Tomi Valkeinen wrote: > On 11/08/2023 19:23, Péter Ujfalusi wrote: >> >> >> On 04/08/2023 13:44, Tomi Valkeinen wrote: >>> The driver has a few places where it does: >>> >>> if (thing_is_enabled_in_config) >>> update_thing_bit_in_hw() >>> >>> This means that if the thing is _not_ enabled, the bit never gets >>> cleared. This affects the h/vsyncs and continuous DSI clock bits. >> >> I guess the idea was to keep the reset value unless it needs to be flipped. >> >>> >>> Fix the driver to always update the bit. >>> >>> Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver") >>> Signed-off-by: Tomi Valkeinen >>> --- >>> drivers/gpu/drm/bridge/tc358768.c | 13 +++++++------ >>> 1 file changed, 7 insertions(+), 6 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c >>> index bc97a837955b..b668f77673c3 100644 >>> --- a/drivers/gpu/drm/bridge/tc358768.c >>> +++ b/drivers/gpu/drm/bridge/tc358768.c >>> @@ -794,8 +794,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) >>> val |= BIT(i + 1); >>> tc358768_write(priv, TC358768_HSTXVREGEN, val); >>> >>> - if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) >>> - tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); >>> + tc358768_write(priv, TC358768_TXOPTIONCNTRL, >>> + (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); >>> >>> /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ >>> val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); >>> @@ -861,11 +861,12 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) >>> tc358768_write(priv, TC358768_DSI_HACT, hact); >>> >>> /* VSYNC polarity */ >>> - if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) >>> - tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); >>> + tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), >>> + (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); >> >> Was this the reverse before and should be: >> (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : BIT(5) > > Bit 5 is 1 for active high vsync polarity. The test was previously > !nvsync, i.e. the same as pvsync. this statement doesn't seem to be true, since this change causes a regression on the Asus TF700T. Apparently, !nvsync is true and pvsync is false in the present case. Best regards, Maxim