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Wed, 14 Oct 2026 07:36:16 -0700 (PDT) X-Received: by 2002:ac5:c001:0:20b0:5e9:4e2b:4c9f with SMTP id 71dfb90a1353d-5e94e2b4d71mr1774536e0c.4.1791988575925; Wed, 14 Oct 2026 07:36:15 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b203839ca1sm1288926a12.11.2026.10.14.07.36.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Oct 2026 07:36:14 -0700 (PDT) Message-ID: <924134e4-946d-40e0-8d93-2951aafda4f9@oss.qualcomm.com> Date: Wed, 14 Oct 2026 16:36:11 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH DNM RFC 13/16] arm64: dts: qcom: sm8650: Describe clock controller power rails To: Dmitry Baryshkov Cc: Konrad Dybcio , Stephen Boyd , Brian Masney , Jerome Brunet , Viresh Kumar , Nishanth Menon , "Rafael J. Wysocki" , Pavel Machek , Len Brown , Greg Kroah-Hartman , Danilo Krummrich , Johan Hovold , Ulf Hansson , Bjorn Andersson , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Mike Tipton , Taniya Das , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, driver-core@lists.linux.dev, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20261014-topic-qc_clk_dvfs-v1-0-3041b788e9f7@oss.qualcomm.com> <20261014-topic-qc_clk_dvfs-v1-13-3041b788e9f7@oss.qualcomm.com> <2ce49c83-b861-4a0d-8412-e8b3ff33bdd5@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=RPQmjIi+ c=1 sm=1 tr=0 ts=6acf9361 cx=c_pps a=1Os3MKEOqt8YzSjcPV0cFA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=7Nn-sgJJM4qzZjt7KU4A:9 a=QEXdDO2ut3YA:10 a=hhpmQAJR8DioWGSBphRh:22 X-Proofpoint-GUID: kVz8TT33oPPEY1PAyQnkFnUUUB940XT5 X-Proofpoint-ORIG-GUID: kVz8TT33oPPEY1PAyQnkFnUUUB940XT5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDA1NyBTYWx0ZWRfX9lYB1eK/cUzH x9gSaTeW+wJfzWZJdB1Mq4xQgCrRBHFfJazRajdpSufdvam1eiZp8f8aJvn3qAcY4Oo7+jywrKW HFKk7OC7lf+wMDnEz1GgLGjeuSyawWnBTblnDXF92FaZzQU9vG1j36JIEALjMvGyLsbbHHA3DeC OkJgWEYNvSu3IS+ukfc2BME8hrMiCWqguV+LtDKHG8ZGdEgyDa0QY1+Nb5sNINfUtRGTO2Ps6fs c5P9xtigQpuBtZxEAU7A90GncX5cjjtKrTmTHn5LMD8Y63TOgGaDN56vCYQEaaP/4E0kZkNV1oo hVxy727jQTeP23Etud0LN3l4g1IhyfMBmkouIBEq3QFHorcgBLAYubMG6Z1d3JHTLMw+zDJ7wgI /gq5TnIX4SFNiE1XFv8la/gfBop6EjVUk6i7hoPNzRCi31Vnu2Ou2QXUNQF8I5exS3NiOBcmnBA c5htMJKSoLPNTf3egLA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDA1NyBTYWx0ZWRfX8SniXG6kpiBd OnmSrWGMQR1YUX/ha3J33QDfZJQGJIlDu5oXW/8y2InCMKAc1zG2Nw9y7R25Di8H7I1f0K0TCqY lgnHCJKn55ID8Zt/nHfk8bbwDgs3qxI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140057 On 10/14/26 4:33 PM, Dmitry Baryshkov wrote: > On Wed, Oct 14, 2026 at 04:20:08PM +0200, Konrad Dybcio wrote: >> On 10/14/26 4:19 PM, Dmitry Baryshkov wrote: >>> On Wed, Oct 14, 2026 at 02:19:13PM +0200, Konrad Dybcio wrote: >>>> From: Konrad Dybcio >>>> >>>> The SM8650 clock-controller nodes omit rails needed by their clocks and >>>> PLLs. Without those connections, the clock-owned DVFS implementation >>>> cannot attach its voters to all required domains and controller probe >>>> can fail before any clocks are registered. >>>> >>>> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") >>>> Assisted-by: LLM >>>> Signed-off-by: Konrad Dybcio >>>> --- >>>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 16 +++++++++++----- >>>> 1 file changed, 11 insertions(+), 5 deletions(-) >>>> >>>> @@ -6049,8 +6055,8 @@ dispcc: clock-controller@af00000 { >>>> <0>, /* dp3 */ >>>> <0>; >>>> >>>> - power-domains = <&rpmhpd RPMHPD_MMCX>; >>>> - required-opps = <&rpmhpd_opp_low_svs>; >>> >>> I think this is neccessary (at least on some platforms) to keep MMCX out >>> of retention. Even if we can drop it here, I don't think we can drop it >>> for older platforms. >> >> MMCX exists precisely to let you turn it off, the clock patches >> retain a way to keep the clock on during the runtime-resume of >> the clock controller driver > > Turning off MMCX is possible together with suspending the dispcc. If > dispcc is resumed, MMCX should be at least low_svs. On some platforms > it's handled by the cmd-db, where MMCX has a minimal value of low_svs. > On other platforms MMCX lists 'RET' as a possible value, however it's > not enough for dispcc (or other CCs) to work. In theory, *I think*, it's > exactly what 'GCC_DISP_AHB_CLK' might need to vote, but we don't > represent it. Retention isn't a ""real"" state the OS should vote for, as the HW downstream of the rails generally needs some flavor of LOW_SVS to function, or at least I don't know of any such cases. See also 7178817f1904 ("pmdomain: qcom: rpmhpd: Skip retention by default") Konrad