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([2a01:e0a:982:cbb0:65eb:d140:2d45:ee85]) by smtp.gmail.com with ESMTPSA id z5-20020a05600c220500b003fba6709c68sm1458806wml.47.2023.07.05.01.53.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Jul 2023 01:53:13 -0700 (PDT) Message-ID: <92b1146c-be79-4d27-0444-cfc2125547e2@linaro.org> Date: Wed, 5 Jul 2023 10:53:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Content-Language: en-US To: Jonathan Marek , freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Kalyan Thota , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list References: <20230704160106.26055-1-jonathan@marek.ca> Organization: Linaro Developer Services Subject: Re: [PATCH] drm/msm/dpu: add missing flush and fetch bits for DMA4/DMA5 planes In-Reply-To: <20230704160106.26055-1-jonathan@marek.ca> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/07/2023 18:01, Jonathan Marek wrote: > Note that with this, DMA4/DMA5 are still non-functional, but at least > display *something* in modetest instead of nothing or underflow. > > Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") > Signed-off-by: Jonathan Marek > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index bbdc95ce374a..52222af5975f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -51,7 +51,7 @@ > > static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19, > CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0, > - 1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT}; > + 1, 2, 3, 4, 5}; > > static const struct dpu_ctl_cfg *_ctl_offset(enum dpu_ctl ctl, > const struct dpu_mdss_cfg *m, > @@ -206,6 +206,12 @@ static void dpu_hw_ctl_update_pending_flush_sspp(struct dpu_hw_ctl *ctx, > case SSPP_DMA3: > ctx->pending_flush_mask |= BIT(25); > break; > + case SSPP_DMA4: > + ctx->pending_flush_mask |= BIT(13); > + break; > + case SSPP_DMA5: > + ctx->pending_flush_mask |= BIT(14); > + break; > case SSPP_CURSOR0: > ctx->pending_flush_mask |= BIT(22); > break; It permits displaying something, but the output is still corrupted on both DMA4 & DMA5, tested with multiple plane sizes and formats. modetest -P 81@93:1080x2400 and modetest -P 87@93:1080x2400 Photo of actual display: https://people.linaro.org/~neil.armstrong/sm8550-dma5.jpg Works fine with DMA2 & DMA3 planes with same parameters. Tested with https://patchwork.freedesktop.org/patch/538277/?series=118074&rev=1, and it doesn't change anything. I think this is still accurate: Tested-by: Neil Armstrong # on SM8550-QRD Thanks, Neil