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Wed, 15 Jan 2025 22:09:50 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50FM9nI0024929 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Jan 2025 22:09:49 GMT Received: from [10.71.108.79] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 15 Jan 2025 14:09:49 -0800 Message-ID: <92b1bd35-28ea-4bf5-82a4-de95f9ffc248@quicinc.com> Date: Wed, 15 Jan 2025 14:09:48 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/35] drm/msm/dpu: enable DPU_WB_INPUT_CTRL for DPU 5.x To: Dmitry Baryshkov , Rob Clark , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio CC: , , , References: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> <20241214-dpu-drop-features-v1-2-988f0662cb7e@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20241214-dpu-drop-features-v1-2-988f0662cb7e@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 06yCehkHFxE5-NTYRmOfEr9QZqcEn9a4 X-Proofpoint-GUID: 06yCehkHFxE5-NTYRmOfEr9QZqcEn9a4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_09,2025-01-15_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 mlxscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=827 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501150158 On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote: > Several DPU 5.x platforms are supposed to be using DPU_WB_INPUT_CTRL, > to bind WB and PINGPONG blocks, but they do not. Change those platforms > to use WB_SM8250_MASK, which includes that bit. > > Fixes: 1f5bcc4316b3 ("drm/msm/dpu: enable writeback on SC8108X") > Fixes: ab2b03d73a66 ("drm/msm/dpu: enable writeback on SM6125") > Fixes: 47cebb740a83 ("drm/msm/dpu: enable writeback on SM8150") > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 +- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > Change LGTM, Reviewed-by: Abhinav Kumar Basically, it means that WB was not validated on those chipsets before enabling them something which should be more strongly enforced moving forward.