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Peter Anvin" , linux-kernel@vger.kernel.org References: <918e147601697b1d4b8f8589f5751e05d6ceccdf.1695371055.git.maciej.wieczor-retman@intel.com> <9751cbaf-8653-d32a-6058-13c251c59b3d@amd.com> <4sxjxe4cgvookcobwbrmsoeszjordi3bpjg22zxut3lanjc46j@xpqt6nblx6uc> <13b360ac-4292-5056-6d00-6eb1d4186b11@amd.com> <8a5d1211-8acb-762d-ae36-bf508b082ef4@intel.com> From: "Moger, Babu" In-Reply-To: <8a5d1211-8acb-762d-ae36-bf508b082ef4@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: DM6PR01CA0014.prod.exchangelabs.com (2603:10b6:5:296::19) To MW3PR12MB4553.namprd12.prod.outlook.com (2603:10b6:303:2c::19) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW3PR12MB4553:EE_|SJ0PR12MB5421:EE_ X-MS-Office365-Filtering-Correlation-Id: 16e5c5b3-40f1-4ceb-3273-08dbc03ffc01 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: We8Ty07xnWFfJhrPWkm2MNw7Pv/Jlnh7afIFAxum0oZmJegI+oWghO/gAPYHp2gPJS5n39P3pJQiZvTjv5tYUuSO5zlrOpiYDq+8WO4E1xoLPhRa3CFvRfyjYwehpaz+/sWLBzUxwtN+YkjjN7oI4QdYv6wzTfwwqrFFN7gcIQ3uxnc1x/FfnDOtFVOGr4Lc3yZhRuKlEwFf/ll9gyNjeX34k9+S2fVDwYyv/gQY2wBZhhMt+pWHzbQYUnIXq2yJcyOFL+kSNkD2W/cobpubI855rGbJ50BW7mutu7XO+7NXbHhdAZgm2ZilJQGDFlu5QAXbakolFeook6XCzTmBP2DSIKOW30p0ZGNpe0OlccDJquZ8AFM97mMKQbn8eQvEf6sk1N4sOSpLn31xv0VTgJLF46skcw8H3jSevoRQGK+9p9zvA+VFINGIu2YRrhgWClB92p+YLjLGU+E6bSvmcksdtsjPHCNF0G+DbFzNoemXTpYbRB/88cPZwR/lNXzSx7YECUvPQDm65zDDEhXpeRK+umAY3t06mZgk4rrtn3Za8Uooz3HuJF1UtSPZMBiVfzmGsfrCaufdvHNcfY8w/iJJeVG6ue5XjO15/LWT4VN/wgppTdwZiNW3A2/QZctq X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MW3PR12MB4553.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(346002)(376002)(396003)(39860400002)(366004)(136003)(230922051799003)(186009)(1800799009)(451199024)(64100799003)(66574015)(6512007)(6506007)(53546011)(83380400001)(86362001)(31696002)(38100700002)(36756003)(2616005)(26005)(2906002)(5660300002)(316002)(7416002)(41300700001)(54906003)(3450700001)(66476007)(66556008)(66946007)(110136005)(966005)(6486002)(31686004)(8936002)(478600001)(8676002)(4326008)(43740500002)(45980500001);DIR:OUT;SFP:1101; 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>>>>> r->cache.shareable_bits = 0xc0000; >>>>> r->cache.min_cbm_bits = 2; >>>>> + r->cache.arch_has_sparse_bitmaps = false; >>>> >>>> Is this change required? >>>> >>>> This is always set to false in rdt_init_res_defs_intel(). >>> >>> The logic behind moving this variable initialization from >>> rdt_init_res_defs_intel() into both cache_alloc_hsw_probe() and >>> rdt_get_cache_alloc_cfg() is that the variable doesn't really have a >>> default value anymore. It used to when the CPUID.0x10.1:ECX[3] and >>> CPUID.0x10.2:ECX[3] bits were reserved. >>> >>> Now for the general case the variable is dependent on CPUID output. >>> And only for Haswell case it needs to be hardcoded to "false", so the >>> assignment makes more sense in Haswell probe rather than in the default >>> section. >> >> Here is the current sequence order with your change. >> >> 1. >> resctrl_late_init -> check_quirks -> __check_quirks_intel -> >> cache_alloc_hsw_probe >> r->cache.arch_has_sparse_bitmaps = false; (new code) >> >> 2. resctrl_late_init -> rdt_init_res_defs -> rdt_init_res_defs_intel >> r->cache.arch_has_sparse_bitmaps = false; (old code) >> >> 3. resctrl_late_init -> get_rdt_resources -> get_rdt_alloc_resources -> >> rdt_get_cache_alloc_cfg >> r->cache.arch_has_sparse_bitmaps = ecx.split.noncont; (new code) >> >> The code in (3) is going to overwrite whatever is set in (1) or (2). >> >> I would say you can just remove initialization in both (1) and (2). That >> makes the code clearer to me. I assume reserved bits in Intel is always 0. >> > > I believe Maciej already addressed this in his response to a similar question > from Peter. Please see: > https://lore.kernel.org/lkml/xnjmmsj5pjskbqeynor2ztha5dmkhxa44j764ohtjhtywy7idb@soobjiql4liy/ The rdt_alloc_capable part is kind of hidden. Now it makes sense. Thanks Babu Moger