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[175.34.62.5]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-339a6ff256dsm17874793a91.16.2025.10.06.16.25.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Oct 2025 16:26:06 -0700 (PDT) Message-ID: <92e05ef2-356b-4c1f-99c3-1e7482775cdc@redhat.com> Date: Tue, 7 Oct 2025 09:25:53 +1000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 09/29] arm_mpam: Add MPAM MSC register layout definitions To: James Morse , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan References: <20250910204309.20751-1-james.morse@arm.com> <20250910204309.20751-10-james.morse@arm.com> Content-Language: en-US From: Gavin Shan In-Reply-To: <20250910204309.20751-10-james.morse@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi James, On 9/11/25 6:42 AM, James Morse wrote: > Memory Partitioning and Monitoring (MPAM) has memory mapped devices > (MSCs) with an identity/configuration page. > > Add the definitions for these registers as offset within the page(s). > > Link: https://developer.arm.com/documentation/ihi0099/latest/ > Signed-off-by: James Morse > Reviewed-by: Ben Horgan > --- > Changes since v1: > * Whitespace. > * Added constants for CASSOC and XCL. > * Merged FLT/CTL defines. > * Fixed MSMON_CFG_CSU_CTL_TYPE_CSU definition. > > Changes since RFC: > * Renamed MSMON_CFG_MBWU_CTL_TYPE_CSU as MSMON_CFG_CSU_CTL_TYPE_CSU > * Whitepsace churn. > * Cite a more recent document. > * Removed some stale feature, fixed some names etc. > --- > drivers/resctrl/mpam_internal.h | 267 ++++++++++++++++++++++++++++++++ > 1 file changed, 267 insertions(+) > > diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h > index 02e9576ece6b..109f03df46c2 100644 > --- a/drivers/resctrl/mpam_internal.h > +++ b/drivers/resctrl/mpam_internal.h > @@ -152,4 +152,271 @@ extern struct list_head mpam_classes; > int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, > cpumask_t *affinity); > > +/* > + * MPAM MSCs have the following register layout. See: > + * Arm Memory System Resource Partitioning and Monitoring (MPAM) System > + * Component Specification. > + * https://developer.arm.com/documentation/ihi0099/latest/ > + */ > +#define MPAM_ARCHITECTURE_V1 0x10 > + > +/* Memory mapped control pages: */ ":" seems unnecessary. > +/* ID Register offsets in the memory mapped page */ > +#define MPAMF_IDR 0x0000 /* features id register */ > +#define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ > +#define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ > +#define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ > +#define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ > +#define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ > +#define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ > +#define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ > +#define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ > +#define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ > +#define MPAMF_IIDR 0x0018 /* implementer id register */ > +#define MPAMF_AIDR 0x0020 /* architectural id register */ > + > +/* Configuration and Status Register offsets in the memory mapped page */ > +#define MPAMCFG_PART_SEL 0x0100 /* partid to configure: */ ":" seems unnecessary. > +#define MPAMCFG_CPBM 0x1000 /* cache-portion config */ > +#define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ > +#define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ > +#define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ > +#define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ > +#define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ > +#define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ > +#define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ > +#define MPAMCFG_PRI 0x0400 /* priority partitioning config */ > +#define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ > +#define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ > + [...] Thanks, Gavin