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Mon, 05 Oct 2026 00:47:28 -0700 (PDT) X-Received: by 2002:a17:903:fa6:b0:2e5:334f:f47e with SMTP id d9443c01a7336-2e5334ff6aamr58114905ad.21.1791186448296; Mon, 05 Oct 2026 00:47:28 -0700 (PDT) Received: from [10.217.217.179] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e5a5cae50fsm3608305ad.25.2026.10.05.00.47.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Oct 2026 00:47:27 -0700 (PDT) Message-ID: <92f75bff-47aa-401f-b232-edaba8fa2061@oss.qualcomm.com> Date: Mon, 5 Oct 2026 13:17:22 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] clk: qcom: mmcc-sdm660: enable the parents of the pixel clock sources To: fabricioakio@gmail.com, Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Konrad Dybcio , AngeloGioacchino Del Regno , Martin Botka Cc: Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261002-sdm660-pclk0-parent-enable-v2-1-b07f6c33e96f@gmail.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20261002-sdm660-pclk0-parent-enable-v2-1-b07f6c33e96f@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA1MDAzMCBTYWx0ZWRfXzMIQ3qZ8AAVt x1VmfnEi2NGwO/b5ryFu5CbqgUKgmM7dIlcAMDrQUva50Ayo85TlkMchhEr+BozK/Ala8+oVefU QUCWWAkht90+JuWkoPPGFa8zKoJTRHQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA1MDAzMCBTYWx0ZWRfX+VKnsXEH+4+h 9qzNRgIlMZdw7xq/SRIO6Hdc8yLcSj576brXV19iKNluo95MSVJCe/IZbqPB0s60fotXKnZUdxJ ac/gsAKtyY8Nl5T4r8ni4gkJGAaB+vZiXQ1WEgtwm/t7PvhZYTbL8nTp4gcSsuI/vyC1lHlDqhf 11ps78fqbCU6j4SIIDnNOxHQkQhC1tEidVb2Rri11LHbDtkcrgr8qWf0kRLiis1p3FR0oae6OmI l550xJCEhPFiroYLIqOjYqCNVkYTBqoAGT4dU4LBcdaL0R4QTHtt9Mr+XvXeQebdz8gMBDES0na lGbNzbM4wLXf/C+5WrzlKF0zqKcHKb+0JO8C8s9LJ8uipujeUryOW7rXCxr5C1aCa1PA/i2kkoc YTDIVqsxVzUREKNfH+LkV66WzS1jNd3eoIi6W3gOijhxYZmZJkqSRemiP5uprcxKyuD8p4IYPTU wCRvgUytRIaw8C43OPA== X-Proofpoint-GUID: 2fCCtCv59QOgmdce6JC9W8KHFcgPTnyU X-Proofpoint-ORIG-GUID: 2fCCtCv59QOgmdce6JC9W8KHFcgPTnyU X-Authority-Analysis: v=2.4 cv=FryQbGrq c=1 sm=1 tr=0 ts=6ac35611 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=V8gMRo3A-47TgN-c6xAA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-05_01,2026-10-02_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610050030 On 10/2/2026 10:16 PM, Fabricio Akio via B4 Relay wrote: > From: Fabricio Akio > > pclk0_clk_src and pclk1_clk_src are fed by the DSI PHY PLLs, which > dsi_pll_14nm_vco_set_rate() resets and only clk_prepare() restarts. The > DSI host sets the link rates before it prepares the PLL, so the RCG is > updated against a stopped source, and if it is enabled at that point > the update times out: > > pclk0_clk_src: rcg didn't update its configuration. > > Seen on a board whose simple-framebuffer node lists the pixel clock: > the RCG then reads enabled at msm's first modeset. > > Set CLK_OPS_PARENT_ENABLE on both so the core prepares the PLL around > the rate change, as dispcc-sm8250 does for its pixel clock sources since > commit acf7a91d0b0e ("clk: qcom: dispcc-sm8250: Enable parents for pixel > clocks"). > > Fixes: 5db3ae8b33de ("clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver") > Signed-off-by: Fabricio Akio Reviewed-by: Taniya Das -- Thanks, Taniya Das