From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F94F48EBFA; Mon, 7 Sep 2026 12:17:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788783436; cv=none; b=aliVzqc8IjBqynbMXKC29OXuOpi4pPV2jAG473dEkE4uROIet0VmVN8JxaCeEyd3BH6cluPr1T6yGqn1LLs4btt3BW7my5YphdRT0DnYxsWUbTJjWef8hqxHRXxxTqkdHNCpWgzeL+l2ts3RH3wTMtb+JicrfgSJG8O/Se80EK0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788783436; c=relaxed/simple; bh=nWBULfK8y2v0QRWjN6ibtoFURwMhy0uin0KZEDFOc/A=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=oN89ny2cgzPQpStid9d8aQT1yLHgmubckOnLH8d9HU7VooPYj3jNQMQ3JF/Z8PSsYsKc4y+FooPdX1p7MOA8F/lMX5nx72MjxKfsgePucZjiWYrItCz/+CtTiaf/0wtVxEKmJ4fx+nT1QkVyR4tRltX4xAXAwDZsVZfy92zP0j8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=US4Y6yRf; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="US4Y6yRf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0AA671F00A3A; Mon, 7 Sep 2026 12:17:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1788783434; bh=EFpyEDVGGTVSZxluvQxTZCLyg4DEZrPQkbjN/ObOnlA=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=US4Y6yRfSLPovFlPMRvrHE4OPetbvdPmaEJ7oH7Rrrb1RcxDOwbt+N5CsuCQHDSkM oLHb/DqPUI9P877SeMvZ88LWMwYsaiCfmvDFBUpcZrYxyDx9WOwXMfSDAOicwxqMkd TbopE+0PBNJgofHYGIJHW8k/jr2+kU/LjTIKRwG/UrX388ohjdKQC1qhs1OcCn8RIt 1kPJqWS72GLQp8OfPOIuk55hiP75KT1Tzc9VHi5+JpkBw7HFITDvBaWpUBqT1cmcHP Y8nb9A05rId9aHKEMowRYbKOMvedhVchF/DNLK8QUDpq98k82XXHXZFd8Esa+p3Zv8 HujZGDMEts5jw== Message-ID: <934b1e87-3ebe-4a6c-a925-6b3993cdcec7@kernel.org> Date: Mon, 7 Sep 2026 14:17:04 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 01/10] ASoC: dt-bindings: qcom,shikra-qaif-cpu: Add binding To: Harendra Gautam Cc: Srinivas Kandagatla , Mark Brown , Liam Girdwood , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Kuninori Morimoto , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Kumpatla , Krzysztof Kozlowski , Sarath Ganapathiraju , Kumar Anurag Singh , Mohammad Rafi Shaik References: <20260903072902.3870009-1-harendra.gautam@oss.qualcomm.com> <20260903072902.3870009-2-harendra.gautam@oss.qualcomm.com> <20260907-arcane-sassy-fennec-afc02a@quoll> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 07/09/2026 13:43, Harendra Gautam wrote: >>> + clock-names: >>> + description: >>> + The first five clocks are always required. Any further entries are the >>> + per-AIF bit clocks (aif_if_ibit), supplied in order starting from >>> + AIF interface 0 for as many serial AIF interfaces as the board uses. >> >> Who provides these clocks? Your example DTS suggests that another SoC >> block, so how these clocks could be optional? Either they are in the >> hardware or they are not. Hardware is not really flexible. > The clocks are provided by the GCC/LPASS clock controller, referenced > via phandles in the DTS example. The distinction between required and > optional is based on usage, not hardware presence. The 5 required > clocks (lpass_config, lpass_core_axim, bus, dma, dma_mem) are needed > for any register access and DMA operation, the hardware block cannot > function without them. The per-interface bit clocks > (aif_if0_ibit..aif_if3_ibit) are only needed when the corresponding > AIF interface is actually used; a board may instantiate QAIF with > fewer than 4 active interfaces, in which case the unused interface > clocks need not be enabled. All four Shikra AIF interface clocks are > listed in the example because Shikra has 4 physical interfaces, but > the binding intentionally allows subsets for future SoCs or board > configurations where not all interfaces are wired up. If the board does not need to enable them, then driver should simply not do that. The clocks are still there, so the clocks are required. Best regards, Krzysztof