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Fri, 26 Sep 2025 07:10:22 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: ANlaf4aDyzkw Date: Fri, 26 Sep 2025 13:09:37 +0200 From: "Arnd Bergmann" To: "Manikanta Guntupalli" , git@amd.com, "Michal Simek" , "Alexandre Belloni" , "Frank Li" , "Rob Herring" , krzk+dt@kernel.org, "Conor Dooley" , =?UTF-8?Q?Przemys=C5=82aw_Gaj?= , "Wolfram Sang" , tommaso.merciai.xr@bp.renesas.com, quic_msavaliy@quicinc.com, Shyam-sundar.S-k@amd.com, "Sakari Ailus" , "'billy_tsai@aspeedtech.com'" , "Kees Cook" , "Gustavo A. R. Silva" , "Jarkko Nikula" , "Jorge Marques" , "linux-i3c@lists.infradead.org" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Linux-Arch , linux-hardening@vger.kernel.org Cc: radhey.shyam.pandey@amd.com, srinivas.goud@amd.com, shubhrajyoti.datta@amd.com, manion05gk@gmail.com Message-Id: <93704e82-ea7d-45ea-8527-8ce92108eccc@app.fastmail.com> In-Reply-To: <20250926105349.2932952-5-manikanta.guntupalli@amd.com> References: <20250926105349.2932952-1-manikanta.guntupalli@amd.com> <20250926105349.2932952-5-manikanta.guntupalli@amd.com> Subject: Re: [PATCH V8 4/5] i3c: master: Add endianness support for i3c_readl_fifo() and i3c_writel_fifo() Content-Type: text/plain Content-Transfer-Encoding: 7bit On Fri, Sep 26, 2025, at 12:53, Manikanta Guntupalli wrote: > Add endianness handling to the FIFO access helpers i3c_readl_fifo() and > i3c_writel_fifo(). This ensures correct data transfers on platforms where > the FIFO registers are expected to be accessed in either big-endian or > little-endian format. > > Update the Synopsys, Cadence, and Renesas I3C master controller drivers to > pass the appropriate endianness argument to these helpers. > > Signed-off-by: Manikanta Guntupalli > Reviewed-by: Frank Li I don't think this is a good interface, based on our discussion so far, and I had hoped you'd change it the way I had suggested with a separate function for the xi3c driver, so normal drivers don't have to worry about the AMD specific quirk. I think this should also avoid mentioning "endianess" in the changelog and in the code itself, since that would likely confuse readers into thinking (as I did in my earlier replies) that this is related to using big-endian kernels. i3c_readl_fifo()/i3c_writel_fifo() are already portable and handle endianess correctly by using the readsl()/writesl() functions. Arnd