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Fri, 29 May 2026 02:23:53 -0700 (PDT) X-Received: by 2002:a17:902:cf03:b0:2bf:25a4:b6d8 with SMTP id d9443c01a7336-2bf25a4b7c9mr14838075ad.10.1780046632888; Fri, 29 May 2026 02:23:52 -0700 (PDT) Received: from [192.168.1.2] ([117.192.250.176]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf23c5c772sm11927515ad.84.2026.05.29.02.23.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 May 2026 02:23:52 -0700 (PDT) Message-ID: <937bc3b3-bd38-4df4-bee9-c68e83de3ff6@oss.qualcomm.com> Date: Fri, 29 May 2026 14:53:45 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/5] clk: qcom: dispcc-qcm2290: Add support for Qualcomm Shikra DISPCC To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain , Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260528-shikra-dispcc-gpucc-v2-0-953f246a0fbb@oss.qualcomm.com> <20260528-shikra-dispcc-gpucc-v2-4-953f246a0fbb@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: YwKWPSMnRgAGcYDMPEQYNvHg9x9wea4G X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTI5MDA5MiBTYWx0ZWRfXw+C6RxQxPTaR f31WC58hNMNtFcwdnE8NLfdljoiJDq7BRAVnTLPGIC3bZYT9jrp0V2CkeUUTz4CpMrjj7hgRuKw 9GjNDIiJnkyW9820+Y/d5qSZ4AKacYxT3Po39r+qORgeCHs7zQ2QruWKmm+0FAym7oDRtJAMm1K VoiQoArd5SCODY1Aivclwd/mGO647cMOOA9LxPWQc097GCZlzwDYOdHRyCEXnuVa/+0NwdV+jD9 jLsaYXBBM2KnqCiSHYzI83ZKPYgOjKlelj3nQ2CPU5ZZWzPvYX9tHObeSIZOULjYxVFfKuQGfun +ruznpWGTYjGOjQXCHHO650+N4ipJK1UkjAiIS0YsRU6+4zQPZl/mOEhQHfZFWgZ2bnmzY5wwrD 2iH5zl3cnbqafKRhZW2qCP36q/lncOzoKfxE5eVJMeBEuKR21ZMMqdon8jgYEhFWvW6bbCZZ7uL LE09Y9aZURSRgl4Bceg== X-Authority-Analysis: v=2.4 cv=DIG/JSNb c=1 sm=1 tr=0 ts=6a195b2a cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=MYhr4v4WboA43l5+MyccHQ==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=M2yKb8xwfWg0M4Fo7NUA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: YwKWPSMnRgAGcYDMPEQYNvHg9x9wea4G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-05-29_02,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 adultscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2605290092 On 28-05-2026 07:12 pm, Dmitry Baryshkov wrote: > On Thu, May 28, 2026 at 03:37:05PM +0530, Imran Shaik wrote: >> The Qualcomm Shikra Display clock controller reuses the QCM2290 DISPCC, >> but has minor differences. Update the parent data of mdss ahb/mdp clocks >> accordingly to the hardware clock plan and correct the GDSC *_wait_val and >> flags which are applicable for both QCM2290 and Shikra SoC, and add the >> support for DSI1 PHY source. >> >> Signed-off-by: Imran Shaik >> --- >> drivers/clk/qcom/dispcc-qcm2290.c | 18 +++++++++++++----- >> 1 file changed, 13 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c >> index 6d88d067337fa132114b0d8666931b449f86de17..19c997f3fe9f197d2c252a9dd1e8169947200f5f 100644 >> --- a/drivers/clk/qcom/dispcc-qcm2290.c >> +++ b/drivers/clk/qcom/dispcc-qcm2290.c >> @@ -2,6 +2,7 @@ >> /* >> * Copyright (c) 2020, The Linux Foundation. All rights reserved. >> * Copyright (c) 2021, Linaro Ltd. >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >> */ >> >> #include >> @@ -32,6 +33,8 @@ enum { >> P_GPLL0_OUT_DIV, >> P_GPLL0_OUT_MAIN, >> P_SLEEP_CLK, >> + P_DSI1_PHY_PLL_OUT_BYTECLK, >> + P_DSI1_PHY_PLL_OUT_DSICLK, >> }; >> >> static const struct pll_vco spark_vco[] = { >> @@ -84,7 +87,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = { >> >> static const struct parent_map disp_cc_parent_map_2[] = { >> { P_BI_TCXO_AO, 0 }, >> - { P_GPLL0_OUT_DIV, 4 }, >> + { P_GPLL0_OUT_MAIN, 4 }, > > Why? > >> }; >> >> static const struct clk_parent_data disp_cc_parent_data_2[] = { >> @@ -101,17 +104,19 @@ static const struct parent_map disp_cc_parent_map_3[] = { >> static const struct clk_parent_data disp_cc_parent_data_3[] = { >> { .fw_name = "bi_tcxo" }, >> { .hw = &disp_cc_pll0.clkr.hw }, >> - { .fw_name = "gcc_disp_gpll0_clk_src" }, >> + { .fw_name = "gcc_disp_gpll0_div_clk_src" }, > > Do you realize that this is an undocumented ABI chance? > >> }; >> >> static const struct parent_map disp_cc_parent_map_4[] = { >> { P_BI_TCXO, 0 }, >> { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, >> + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, >> }; >> >> static const struct clk_parent_data disp_cc_parent_data_4[] = { >> { .fw_name = "bi_tcxo" }, >> { .fw_name = "dsi0_phy_pll_out_dsiclk" }, >> + { .fw_name = "dsi1_phy_pll_out_dsiclk" }, >> }; >> >> static const struct parent_map disp_cc_parent_map_5[] = { >> @@ -153,8 +158,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { >> >> static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { >> F(19200000, P_BI_TCXO_AO, 1, 0, 0), >> - F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0), >> - F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0), >> + F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), >> + F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), > > Why? It's not mentioned in the commit message. > As per the HW clock plan, the ahb(parent_*_2)/mdp(parent_*_3) clock RCG parent must be GPLL0_OUT_MAIN (gcc_disp_gpll0_div_clk_src). Updated them accordingly and mentioned the same in the commit text below: "Update the parent data of mdss ahb/mdp clocks accordingly to the hardware clock plan" Will move these to indices approach, and add in a separate commit as you mentioned in the other patch comment. >> { } >> }; >> >> @@ -450,11 +455,14 @@ static const struct qcom_reset_map disp_cc_qcm2290_resets[] = { >> >> static struct gdsc mdss_gdsc = { >> .gdscr = 0x3000, >> + .en_rest_wait_val = 0x2, >> + .en_few_wait_val = 0x2, >> + .clk_dis_wait_val = 0xf, >> .pd = { >> .name = "mdss_gdsc", >> }, >> .pwrsts = PWRSTS_OFF_ON, >> - .flags = HW_CTRL, >> + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, > > And this also needs explanation. > Sure, will add these GDSC fixes in separate commit in next series. Thanks, Imran >> }; >