Re: [PATCH 1/2] clk: qcom: gcc-ipq5018: drop CLK_SET_RATE_PARENT from ubi0_axi_clk_src

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 10/2/26 2:19 PM, Andrei-Alexandru Bleortu wrote:
> ubi0_axi_clk_src has CLK_SET_RATE_PARENT, but its parents are XO and
> the read-only GPLL0 and GPLL2 post-dividers, so propagating a rate
> request can never change their rate.
> 
> It does make the clock core treat any rounding gap as a GPLL0 rate
> change. Requesting 400 MHz (GPLL0 / 2) while GPLL0 reads back as
> 799999998 Hz makes GPLL0 the top of the change, and clk_change_rate()
> then re-runs set_rate on every GPLL0 consumer. That includes the live
> NoC clocks and sdcc1_apps_clk_src, which is gated at that moment and
> fails with "rcg didn't update its configuration", leaving the eMMC
> controller and the board hung.
> 
> Drop the flag so that a rate request on ubi0_axi_clk_src stays local to
> it. gcc_ubi0_axi_clk keeps its flag and still forwards requests to this
> clock.
> 
> Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
> 
> Assisted-by: LLM
> Signed-off-by: Andrei-Alexandru Bleortu <me@andrei-z.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad