From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E26F34C806 for ; Wed, 10 Jun 2026 18:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781114931; cv=none; b=qwFYh7QqfiwcrND6/kneKpZYQw0QQIG3kNKZMMhP4KG5/kBaCHhzBTbbVaPFOAUz2KNSlXgEfVMDPefe5kkllDILQSqMoSOUX1WLUQRMAQQYJqemKNLfn6NJaDyhzLoOJrdgczDsf+dau+UaPGfbzm6XsmIAbRMaHNP9PQ/RRio= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781114931; c=relaxed/simple; bh=MiwGDwq8J0dYXEcvwkbwqi1QsuSnGPEN5WqLtWs7JOk=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Le5zl1ohXqWIsF2cQta3doUoMoFFDwzckgfuzLk8jiHmGCFs3vJp+Bw3HHV+dxQIhV1r4DERPwJe6D26rR0oj0VfdygKJ0OM80qCl/n0Td/a9n8PlII5EZ+9tpqS04TeHkFqkcGdpf8FYLUM+aimnXBjkOqSa5Pizwso1cR1Z48= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=fERRfb6O; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Gf7pVJvd; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="fERRfb6O"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Gf7pVJvd" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65AFwpFg2042077 for ; Wed, 10 Jun 2026 18:08:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= bXZTlyKOD1gEIcmRjq7Xyk4ej9sDT+UAFKDVbpdbWd8=; b=fERRfb6O+xaaTLz/ foaZYn3Q7ZfJcBfUWu4Ozk5yPpWtKIMRXRcjgKV2k2plPxJKJX/wNszI2vec+Nh5 mCIeqkelEvlLA5h+85uxKALlpQjM4oFVa6HkEa7RSdh58xEezpGpOoKhrVvM94Hx 1PkgxGi42KxCggsjYt2k1WCSRlshE/dNLS4n/kiq85q8lysat+DreBPzw4LW1Pdu 5Mu5ycGbIZHeZjTsgDRs1ggo24fE7yFbKv3zUq7PJebmsOfKgjAayf/k2MjsXuuS 5eM2GkGACik9TfWpGLGYzwdQ77NA+3WRznfTKsAt2qRWAmX/XXWefl8P0WU7kT+A 79CuVw== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4epukevkkc-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 10 Jun 2026 18:08:49 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-36d97415004so13608323a91.2 for ; Wed, 10 Jun 2026 11:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1781114928; x=1781719728; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=bXZTlyKOD1gEIcmRjq7Xyk4ej9sDT+UAFKDVbpdbWd8=; b=Gf7pVJvdtk87Rnyk/4mApFVVgC4LTMbJnQZzJbSSv77rOhimrjyw90XiR3X7o4mXHc JNoI39vjg0A7LjAZHl08c/40xVNb09fD2f7j6RgUkA5FkVuONWAEdlgsjUNgvs1RXKAz qxfOmQL+wXKEg+SGlcUG+UCL3V5BQ5j9yt6oL1wCgUrBF3hqvmW63ZLSnpMrZ1IsYiG9 2KohnWU8CL5g/DRNbOR7JbNVTgPtzJcRzBwJiMX3myrqcDHrVkH5ZZH5uPl11Cxd2xCb SOPtl7UiYwBHWQKNyZYsURIAQhkx+MtbxAaNIxYPxOS/pWzvZ6dSbkKcSne+wxeNzL19 FQPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781114928; x=1781719728; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=bXZTlyKOD1gEIcmRjq7Xyk4ej9sDT+UAFKDVbpdbWd8=; b=nqzFS3r8V3/j6FVRjagLuo9+ZrywlFfMDdEdOp/X2KPpKAfLBsS74FhueGpVmoNNWW IpZSegTTvqr8dFhzvTIHhDMravjAGN2IKhfn8d2h5h5I+kJI7sNlWuWR01HYr5qUWq18 fwP1NMa7TGR9jLWkQQ7FgRybacT+HD+40/at5LTh+oh3MyOwftRt7UauCoThpMmJ95Ut nHLhTFeOMXBdBQWCXPfgpGjVzIGhu7BXwZwgjYgEpMa/KdBz7Y725fHyQn3UAsjrPgkJ VpSOEhmOYuZEns7s06iAXJn1+5RS4gwTMr6z9sfowmEK3uOWXA+C+IXLf8gcfUkHN69z 2m8A== X-Forwarded-Encrypted: i=1; AFNElJ+f5i4A9wJqP7KnA0g5wMplbVu8iKI0MtKPsdHm6TESWnirLe7n2AsRj8AI+QyHF0VfcEH0KEBEtROJKBU=@vger.kernel.org X-Gm-Message-State: AOJu0Yy+2J4ArtUQy904pqPMgVKi4o/9MI29Qnc1SEz8QR4l24qxOaKE tMMO4NNm3HMAoiI0aKsSpVDuqbzos3BDu0M05PHjYLSM0TGiA47S+zqR9mWd5xMMpCm7ethVhuV QlQ2d++e7TI1lbBAmS7uumewV4LckVAeMuLGZrRQIVsOXmoZLsO6n6SqGO6FL02GOtzg= X-Gm-Gg: Acq92OG1CIQ6inzeTspxvuXKaqg6jyaAAm1wpgZVy0sxq8ZyK64nmoM/5U0I0Rpo5GX OqpIVo0DV7EHWiL3LdLceQ6n3es4oTIUyzfRA6C1PnYsappsiAYpPZ/gpvbrJbSnDJyM4oNow9m fhqp92PrZA27R4kNH/NSGz2ED9yCST3qUaU0an6neENWrg8bUIAA16eHqydzTh1ZUUYDT37i4Bq bZOF8JwrrZzpEYrXO/ZCY7XAm8SrCTAGW8z9SsODaiXcLj/Wi0EVMu7K0XI5kZHcUUWzTmdxs+G z0BOqo8VGnOG8K5bl2FKhFmBMEWPXl0jt25sSp5SJKvzzkBMpjngxJpeMFGBM4pdwfVzbwY0bin frQe/CVgVSmoY/veIg6dmXkpzjyoSfcQ/WcdDI+FUIDKjmfctnTcspoLurp88 X-Received: by 2002:a17:902:ea0a:b0:2c0:db23:4a4 with SMTP id d9443c01a7336-2c2da80b9b6mr3538355ad.36.1781114927959; Wed, 10 Jun 2026 11:08:47 -0700 (PDT) X-Received: by 2002:a17:902:ea0a:b0:2c0:db23:4a4 with SMTP id d9443c01a7336-2c2da80b9b6mr3538105ad.36.1781114927490; Wed, 10 Jun 2026 11:08:47 -0700 (PDT) Received: from [192.168.1.8] ([122.174.150.90]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f6d1e5sm239164985ad.12.2026.06.10.11.08.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Jun 2026 11:08:47 -0700 (PDT) Message-ID: <93a55513-b09c-47a6-bd3b-cfed25ca7a70@oss.qualcomm.com> Date: Wed, 10 Jun 2026 23:38:42 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] pinctrl: qcom: lpass-lpi: drop unused runtime-PM write helper To: Bjorn Andersson , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Nathan Chancellor References: <20260610180012.3505877-1-ajay.nandam@oss.qualcomm.com> Content-Language: en-US From: Ajay Kumar Nandam In-Reply-To: <20260610180012.3505877-1-ajay.nandam@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDE3MCBTYWx0ZWRfXxygFtmq9aWN5 OidfgnKRF49cQtZw2TlFqAsQ/DvfREeW/4zG5n4vztgoE5ZkBrOrLhH1WSuXTS1bQgpoFHjMP5x XreJQGDxpFhkWKr0ZMh+Jcc23xOoew3qNiqQBcdD8E50k49xwEJXLgzKY5jhChWz8pNie33OCah TR8NhfXqdKVolFGm2sB/fxvKKIf2F3BkR/dmCIi/f6cekq3Lnxai4ndWWW+CkNyyAIxW6U45rLQ Sk2RpMxpzdteKR/jdycRV3wx/i7s6vlbjFSpJ93t1iovbJ+dS+fVXQEK+wpMp55qxhLbasf7zY4 hFiSouwSvf87AnRr7flvMjPb8KPv08UkfnD20mNYkKSuf0sG8RbK81XurUEzeoNmzz67YD0KA8o tGy63zUmOSSsw2PW1IXeK7tqle8qUvQI6TeNi5skHd5gl18M93Fn3ZGAbA4H2j7gIGRiTdV3mrL LkEabQ45ZKR8bnMaW7Q== X-Proofpoint-ORIG-GUID: bZYBBj9KU0yg2v9_Cy5RydvgrADpxi1S X-Proofpoint-GUID: bZYBBj9KU0yg2v9_Cy5RydvgrADpxi1S X-Authority-Analysis: v=2.4 cv=DNG/JSNb c=1 sm=1 tr=0 ts=6a29a831 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ph9GlEvSy1Vz2RjkXBjw8g==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=byEZ703KndBbruZr8VwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_03,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100170 Hi Bjorn, Thanks for the report and for carrying this in linux-next. Root cause was an unused static wrapper (lpi_gpio_write()) left after the PM clock conversion. I’ve posted v2 here: https://lore.kernel.org/all/20260610180012.3505877-1-ajay.nandam@oss.qualcomm.com/ v2 removes the dead wrapper, keeps behavior unchanged, and also addresses follow-up naming/style feedback. Thanks, Ajay On 6/10/2026 11:30 PM, Ajay Kumar Nandam wrote: > lpi_gpio_write() became unused after the PM clock runtime conversion > switched write paths to register helper calls inside callers that already > hold an active runtime-PM reference. > > With -Werror this triggers: > error: 'lpi_gpio_write' defined but not used [-Wunused-function] > > Drop the dead wrapper and rename the low-level MMIO helpers from > __lpi_gpio_* to lpi_gpio_*_reg for neutral register-accessor naming. > > Fixes: b719ede389d8 ("pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM") > Reported-by: Nathan Chancellor > Closes: https://lore.kernel.org/all/f03850f6-186d-4988-a450-e6e95f24a551@kernel.org/ > Signed-off-by: Ajay Kumar Nandam > --- > drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 50 +++++++++--------------- > 1 file changed, 18 insertions(+), 32 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > index 4d758fd117c4..5fd4a4eba654 100644 > --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c > @@ -52,15 +52,15 @@ static void __iomem *lpi_gpio_reg(struct lpi_pinctrl *state, > return state->tlmm_base + pin_offset + addr; > } > > -static void __lpi_gpio_read(struct lpi_pinctrl *state, > - unsigned int pin, unsigned int addr, u32 *val) > +static void lpi_gpio_read_reg(struct lpi_pinctrl *state, > + unsigned int pin, unsigned int addr, u32 *val) > { > *val = ioread32(lpi_gpio_reg(state, pin, addr)); > } > > -static void __lpi_gpio_write(struct lpi_pinctrl *state, > - unsigned int pin, unsigned int addr, > - unsigned int val) > +static void lpi_gpio_write_reg(struct lpi_pinctrl *state, > + unsigned int pin, unsigned int addr, > + unsigned int val) > { > iowrite32(val, lpi_gpio_reg(state, pin, addr)); > } > @@ -74,21 +74,7 @@ static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, > if (ret < 0) > return ret; > > - __lpi_gpio_read(state, pin, addr, val); > - > - return pm_runtime_put_autosuspend(state->dev); > -} > - > -static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, > - unsigned int addr, unsigned int val) > -{ > - int ret; > - > - ret = pm_runtime_resume_and_get(state->dev); > - if (ret < 0) > - return ret; > - > - __lpi_gpio_write(state, pin, addr, val); > + lpi_gpio_read_reg(state, pin, addr, val); > > return pm_runtime_put_autosuspend(state->dev); > } > @@ -150,7 +136,7 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, > return ret; > > guard(mutex)(&pctrl->lock); > - __lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG, &val); > + lpi_gpio_read_reg(pctrl, pin, LPI_GPIO_CFG_REG, &val); > > /* > * If this is the first time muxing to GPIO and the direction is > @@ -160,23 +146,23 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, > */ > if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && > !test_and_set_bit(group, pctrl->ever_gpio)) { > - __lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); > + lpi_gpio_read_reg(pctrl, group, LPI_GPIO_VALUE_REG, &io_val); > > if (io_val & LPI_GPIO_VALUE_IN_MASK) { > if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) > - __lpi_gpio_write(pctrl, group, > - LPI_GPIO_VALUE_REG, > - io_val | LPI_GPIO_VALUE_OUT_MASK); > + lpi_gpio_write_reg(pctrl, group, > + LPI_GPIO_VALUE_REG, > + io_val | LPI_GPIO_VALUE_OUT_MASK); > } else { > if (io_val & LPI_GPIO_VALUE_OUT_MASK) > - __lpi_gpio_write(pctrl, group, > - LPI_GPIO_VALUE_REG, > - io_val & ~LPI_GPIO_VALUE_OUT_MASK); > + lpi_gpio_write_reg(pctrl, group, > + LPI_GPIO_VALUE_REG, > + io_val & ~LPI_GPIO_VALUE_OUT_MASK); > } > } > > u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); > - __lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); > + lpi_gpio_write_reg(pctrl, pin, LPI_GPIO_CFG_REG, val); > > return pm_runtime_put_autosuspend(pctrl->dev); > } > @@ -337,17 +323,17 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, > guard(mutex)(&pctrl->lock); > if (output_enabled) { > val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); > - __lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); > + lpi_gpio_write_reg(pctrl, group, LPI_GPIO_VALUE_REG, val); > } > > - __lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG, &val); > + lpi_gpio_read_reg(pctrl, group, LPI_GPIO_CFG_REG, &val); > > u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); > u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), > LPI_GPIO_OUT_STRENGTH_MASK); > u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); > > - __lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); > + lpi_gpio_write_reg(pctrl, group, LPI_GPIO_CFG_REG, val); > > return pm_runtime_put_autosuspend(pctrl->dev); > }