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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa68c4e3749sm662769566b.154.2024.12.13.02.13.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Dec 2024 02:13:45 -0800 (PST) Message-ID: <93c75fdd-c09e-4fe3-b79f-fea8cd08ec0b@oss.qualcomm.com> Date: Fri, 13 Dec 2024 11:13:44 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: qcom: Add coresight nodes for QCS8300 To: Jie Gan , Konrad Dybcio , "Aiqun Yu (Maria)" , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241205084418.671631-1-quic_jiegan@quicinc.com> <16efb6a8-ecaf-4097-ac5f-368ebab177a8@quicinc.com> <25a410a7-2418-45bd-be06-3672a9fb1928@quicinc.com> <04d23c55-9167-4e8a-9e5b-6dcf66b02b8f@oss.qualcomm.com> <409678b0-339e-4d93-86f1-117d358a2d33@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <409678b0-339e-4d93-86f1-117d358a2d33@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 2-T9rzM0iV4mDaJMnaaBwOgtSRpoQN0g X-Proofpoint-GUID: 2-T9rzM0iV4mDaJMnaaBwOgtSRpoQN0g X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130069 On 13.12.2024 2:42 AM, Jie Gan wrote: > > > On 12/13/2024 8:35 AM, Konrad Dybcio wrote: >> On 9.12.2024 3:01 AM, Jie Gan wrote: >>> >>> >>> On 12/8/2024 12:28 AM, Aiqun Yu (Maria) wrote: >>>> >>>> >>>> On 12/5/2024 4:44 PM, Jie Gan wrote: >>>>> Add following coresight components for QCS8300 platform. >>>>> It includes CTI, dummy sink, dynamic Funnel, Replicator, STM, >>>>> TPDM, TPDA and TMC ETF. >>>>> >>>>> Signed-off-by: Jie Gan >>>>> --- >>>>> Changes in V2: >>>>> 1. Rebased on tag next-20241204. >>>>> 2. Padding the register address to 8 bits. >>>>> Link to V1 - https://lore.kernel.org/linux-arm-msm/20240929-add_coresight_devices_for_qcs8300-v1-1-4f14e8cb8955@quicinc.com/ >>>>> --- >>>>>    arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2150 +++++++++++++++++++++++++ >>>>>    1 file changed, 2150 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>>> index 73abf2ef9c9f..eaec674950d8 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >>>>> @@ -293,6 +293,18 @@ system_sleep: domain-sleep { >>>>>            }; >>>>>        }; >>>>>    +    dummy_eud: dummy-sink { >>>>> +        compatible = "arm,coresight-dummy-sink"; >>>>> + >>>>> +        in-ports { >>>>> +            port { >>>>> +                eud_in: endpoint { >>>>> +                    remote-endpoint = <&swao_rep_out1>; >>>>> +                }; >>>>> +            }; >>>>> +        }; >>>>> +    }; >>>>> + >>> >>> [...] >>> >>>>> + >>>>> +        tpdm@482c000 { >>>>> +            compatible = "qcom,coresight-tpdm", "arm,primecell"; >>>>> +            reg = <0x0 0x0482c000 0x0 0x1000>; >>>>> + >>>>> +            clocks = <&aoss_qmp>; >>>>> +            clock-names = "apb_pclk"; >>>>> + >>>>> +            qcom,dsb-element-bits = <32>; >>>>> +            qcom,dsb-msrs-num = <32>; >>>>> +            status = "disabled"; >>>> >>>> Could you please provide more detailed information on why some TPDM >>>> nodes are disabled by default while others are not? >>> Some of TPDM nodes are disabled by default because the one of the following reasons: >>> 1. TPDM device are designed to generate HW events, it needs a clock source to read&write its registers. Coresight driver cannot control the clock source ouside AP core, so those TPDM devices without enabled clock source will crash device in probe. >>> 2. Some of TPDM devices can't bootup with fused devices. >>> 3. Some of TPDM devices have known hardware issues that not resolved. >>> >>> I put those disabled TPDM devices in DT in case some of them may be "fixed" in future. >> >> Please mark them as >> >> /* Hardware issues */ >> status = "fail"; >> > > Maybe I should remove these devices, to avoid confusion. Is that ok? That works as well Konrad