From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Sivansh Gupta <sivansh.gupta@oss.qualcomm.com>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Cc: Jassi Brar <jassisinghbrar@gmail.com>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] mailbox: qcom-cpucp: read mbox hardware register using readq()
Date: Thu, 17 Sep 2026 10:07:12 +0200 [thread overview]
Message-ID: <93ce8588-7500-45da-9b9a-424c202590cf@oss.qualcomm.com> (raw)
In-Reply-To: <20260915093910.2487018-1-sivansh.gupta@oss.qualcomm.com>
On 9/15/26 11:39 AM, Sivansh Gupta wrote:
> Mailbox hardware registers are 64 bit wide, but the interrupt handler
> currently reads only 32 bits with readl() at 0x4 offset (upper 32
> bits). This does not return the correct value expected by PDP log
> driver. Reading the register with readq() at the base address
> returns the correct value expected.
This is a valid reason, but that driver doesn't exist upstream..
If you believe it'd be beneficial, please upstream it. For now,
please focus the reasoning on the actual data being lost, not on
some out-of-tree driver having issues with that
Konrad
prev parent reply other threads:[~2026-09-17 8:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-08 15:50 [PATCH] " Sivansh Gupta
2026-09-09 6:20 ` Sibi Sankar
2026-09-15 9:39 ` [PATCH v2] " Sivansh Gupta
2026-09-17 8:07 ` Konrad Dybcio [this message]
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