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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a0763d8sm736128266b.2.2025.08.04.05.24.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Aug 2025 05:24:41 -0700 (PDT) Message-ID: <93fc49a1-ce8f-447a-9208-251e74d4bf88@oss.qualcomm.com> Date: Mon, 4 Aug 2025 14:24:37 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller To: Varadarajan Narayanan , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, ilia.lin@kernel.org, djakov@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Cc: Sricharan Ramabadhran , Md Sadre Alam References: <20250804112041.845135-1-quic_varada@quicinc.com> <20250804112041.845135-3-quic_varada@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250804112041.845135-3-quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=JOM7s9Kb c=1 sm=1 tr=0 ts=6890a68a cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=276k8YKwey--yEOqDJUA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: UyzHMAI3Sdn-ADRz7DCgz716ALyh0zUI X-Proofpoint-ORIG-GUID: UyzHMAI3Sdn-ADRz7DCgz716ALyh0zUI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODA0MDA2OCBTYWx0ZWRfXxE5kovexmVkb SVvFpw/QECH9ZPymwLzwERdo3lXkT5Atf/iuDUftJdZA1AQ18DrpOr7JU7u7qbIh0YU8NI1WGVP eJ0Uwhihwws0PCZRCX4E/7kVnpeNXEKYtLCXJ7hjRYyEAgbocRqE5UFAmQCdGfwcqSbIMTYr7v5 hVb/qNIgFFNeVbup9Wn6gZVBbBwelcetNNNfEQv/YTFf/isdMNHYSCJH0PigS0OOwNSGDlaDYVp 9aHkcE4mtL5D2DRHaEJDxKoad2PAYj5CMeDim/rq247vJKII8eAK7Bo088h8RvufZxXpLkG8mjH v+qm3BM66gUXxDWK3I4GukFSLBrz3l5wNNMEA2CGFgkWfloT9O8WHAZrWo4y3fEMm5b99FVhziC rjTP/cPZEaLXV2xrNKANKaYh4NteaWVP9w8UT718Atgv+qMQXoc1La8rBZInd9HbeEbjrHB/ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-04_05,2025-08-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508040068 On 8/4/25 1:20 PM, Varadarajan Narayanan wrote: > From: Sricharan Ramabadhran > > CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support. > Add support for the APSS PLL, RCG and clock enable for ipq5424. > The PLL, RCG register space are clubbed. Hence adding new APSS driver > for both PLL and RCG/CBC control. Also the L3 cache has a separate pll > and needs to be scaled along with the CPU and is modeled as an ICC clock. > > Co-developed-by: Md Sadre Alam > Signed-off-by: Md Sadre Alam > Signed-off-by: Sricharan Ramabadhran > [ Removed clock notifier, moved L3 pll to icc-clk, used existing > alpha pll structure ] > Signed-off-by: Varadarajan Narayanan > --- [...] > +static struct clk_alpha_pll ipq5424_apss_pll = { > + .offset = 0x0, > + .config = &apss_pll_config, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], > + .flags = SUPPORTS_DYNAMIC_UPDATE, > + .clkr = { > + .enable_reg = 0x0, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "apss_pll", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_XO, > + }, > + .parent_names = (const char *[]){ "xo-board-clk"}, Parent_data and parent_names are mutually exclusive [...] > + .num_parents = 1, > + .ops = &clk_alpha_pll_huayra_ops, > + }, > + }, > +}; > + > +static const struct clk_parent_data parents_apss_silver_clk_src[] = { > + { .index = DT_XO }, > + { .index = DT_CLK_REF }, > + { .hw = &ipq5424_apss_pll.clkr.hw }, > +}; You use indices here /\ [...] But not here \/ > +static struct clk_alpha_pll ipq5424_l3_pll = { > + .offset = 0x10000, > + .config = &l3_pll_config, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_2290], > + .flags = SUPPORTS_DYNAMIC_UPDATE, > + .clkr = { > + .enable_reg = 0x0, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "l3_pll", > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xo-board-clk", > + }, > + .parent_names = (const char *[]){ "xo-board-clk"}, > + .num_parents = 1, > + .ops = &clk_alpha_pll_huayra_ops, > + }, > + }, > +}; > + > +static const struct clk_parent_data parents_l3_clk_src[] = { > + { .fw_name = "xo-board-clk" }, > + { .fw_name = "clk_ref" }, > + { .hw = &ipq5424_l3_pll.clkr.hw }, > +}; [...] > + .hw.init = &(struct clk_init_data){ > + .name = "l3_clk", > + .parent_hws = (const struct clk_hw *[]){ "clk_hw *[]) {" Konrad