From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F398F1E0DB0; Wed, 29 Jan 2025 18:36:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738175814; cv=none; b=UUpohSYLTDaH8gQqe35l0kimvw3HEvaBeeGkTzIrt59nbtmHozbAvi91+EbJW0Up9UBC4XMd4KPzbX6NoZJvo1H8xJGLjpLZXJtBqZKLPFkD7nMcDFgLECeSl/Ryh3xE+zVDcEb2uuEAuwahtsm+2u/OgFsCkK8DseseHR6josU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738175814; c=relaxed/simple; bh=3s5q/IB36iLF+fgbPT+DSVq5osOvk8zyrWzKch9Ke6c=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=LQbNao3b8qENz6h3csYmrkTj1z2TdX/MTXZWpT7gUxcGIiQVVfAjUgdV7pkRcgl91YMFkq0kY5pnbPpX3JmlyeXW7ziaLaKPHhjjD4EQwflrrzw96lQ5cq1+A1GbZrSiAHb5D6ELadmkw6l2tA7/2vzdPlyUr62VRDsy2cicn/g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Pls+6dNw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Pls+6dNw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39931C4CED1; Wed, 29 Jan 2025 18:36:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738175813; bh=3s5q/IB36iLF+fgbPT+DSVq5osOvk8zyrWzKch9Ke6c=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Pls+6dNwHxJNuY1+O45iN5J3G5bgjzaK6Bf+537nZWRjpHsB2luuyLoDMA/+EseWC 5EqCOFaLj+zw8h82Fju+yKGvVlSFHFtqtMuIts49EXmoWY2q/7kPYurdCtQtQ7cMVp CAS2T4dAF7O26PTdtnFKTvnow0NNdvxNfGavawLWpRJqAHA0xjkl6vQoDvEjEDWYe5 a/LEvswOHUch/PBbq08Nd9MeLWikRUcFutsYUUsOANzhf60tL97ltNWgRTxmHNk/1z hDMnz69EKrloeKh1XpNlLie2ZbQ4ZNFJcNMjDRa9aGoaxjeXLbXH3h6gFMxFuLy8Z2 T4ZiJLSZ5lWYw== Message-ID: <94055d48-0b04-4b1b-b38c-cc5666bcccc9@kernel.org> Date: Wed, 29 Jan 2025 19:36:48 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 12/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H SoC To: Thierry Bultel , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> <20250129165122.2980-13-thierry.bultel.yh@bp.renesas.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 29/01/2025 17:37, Thierry Bultel wrote: > Add the initial dtsi for the RZ/T2H Soc: > > - gic > - armv8-timer > - cpg clock > - sci0 uart > > also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps > all 4 CPUs enabled, for consistency with later support of -m24 > and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively, > and that will use /delete-node/ to disable the missing CPUs. > > Signed-off-by: Thierry Bultel > --- > arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 129 ++++++++++++++++++ > arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi | 8 ++ > 2 files changed, 137 insertions(+) > create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077.dtsi > create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > new file mode 100644 > index 000000000000..55a2b1bd8100 > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi > @@ -0,0 +1,129 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/T2H SoC > + * > + * Copyright (C) 2025 Renesas Electronics Corp. > + */ > + > +#include > +#include > + > +/ { > + compatible = "renesas,r9a09g077"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + extal: extal { Use some generic clock names, prefixes or suffixes. > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + loco: loco { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + /* This value must be overridden by the board */ > + clock-frequency = <0>; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + L3_CA55: cache-controller-0 { Labels are lowercase. > + compatible = "cache"; > + cache-unified; > + cache-size = <0x100000>; > + cache-level = <3>; > + }; ... > diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi > new file mode 100644 > index 000000000000..f54bb50829db > --- /dev/null > +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +/* > + * Device Tree Source for the RZ/T2H 4-core SoC > + * > + * Copyright (C) 2025 Renesas Electronics Corp. > + */ > + > +#include "r9a09g077.dtsi" What is the point of this DTSI file? What is the point of your top-level compatibles if you do not use them? Best regards, Krzysztof