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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: AgzcXAsgiTiBVgizQzlFlOUvkZufX4Xx X-Proofpoint-ORIG-GUID: AgzcXAsgiTiBVgizQzlFlOUvkZufX4Xx X-Authority-Analysis: v=2.4 cv=HqVG3UTS c=1 sm=1 tr=0 ts=6a4cd429 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=_qhDSAx7fSPv64GxxyMA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA3MDEwMCBTYWx0ZWRfX09JZUrTE8XJ6 RpK7fC/fmPlU+K1Xf8vA/joFEms9h43EvzfJcESTdFuI6JYTcb4ksmrzF6MmFeZKWbO88I9EDbv ECzTbjA0vNcYh9m0Y7cm2+90GMoYwxULzH+Iyo0xnGK1UZyg2gQKH3tzmVaoHpdHCeNbvIzL889 rvukALdChWJ00wgc496dTN3DvN2dn/6kWtASyA2VKFOL5XGww6oZWI6IrngtXqHLCmC24i9NHJh Y1z0pK5IX1lHB/97mE9PqiQB3helqRV4/+RyCFYKQeYCJ3i1SRHiMfCdgSJEAws0CEzV/aR2P1j BT2oxSjqEvi27Oi7fkTZBdnPwl2uA4NLrQzQdv2H8/P7/I7p2Qma8Hu2WvHPvcrx75QUP/can+8 T+aSRWuVNcTafLDFe9fnz62MHUM5oLaIQpqdOf6BcwGZDB5QRa/O7Z5MjeFbqWViO63uqOO/PNI 1PF+tkVoVbJnAkBATTA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA3MDEwMCBTYWx0ZWRfX2B3nhy48fTbe sSJqbF73Fr1Sme9MhMiDQMfK2tphzcMllcQh1312LJio9LKnAV/NkuhrPirvGN5BYu2dlHvU34v NQnlRoUqDUh3ldC8vehDG9lN/X6cHuw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-07_02,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 adultscore=0 suspectscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607070100 On 6/26/26 5:15 PM, Abel Vesa wrote: > On 26-06-26 09:46:03, Krishna Chaitanya Chundru wrote: >> >> >> On 6/25/2026 3:42 PM, Abel Vesa wrote: >>> On 26-06-10 17:40:09, Krishna Chaitanya Chundru wrote: >>>> Eliza supports two PCIe instances: one 8GT/s x1 (PCIe0) and one 8GT/s x2 >>>> (PCIe1). Add PCIe controller and PHY nodes for both instances, and update >>>> the GCC clock references to use the newly added PHY nodes instead of >>>> placeholder zeros. >>>> >>>> Signed-off-by: Krishna Chaitanya Chundru >>>> --- [...] >>> No pinctrl states? >> As we are adding perst & wake gpio's in board specific file, it is better to >> add the pincntrl also >> there only. > > I'll let Bjorn and Konrad reply, but most of the sm8*50.dtsi have > them. Though some of the newer platforms moved them in the board dts. Some folks argue (I believe purely ideologically) that the pin states should be defined in the board DTSI, but I don't think we have a single example of non-default routing in the many many years of linux-arm-msm, so I think the reasonable decision is to keep them in the SoC DTSI. Konrad