From: David Laight <David.Laight@ACULAB.COM>
To: 'Mark Rutland' <mark.rutland@arm.com>, Ard Biesheuvel <ardb@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Frederic Weisbecker <frederic@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
James Morse <james.morse@arm.com>,
Quentin Perret <qperret@google.com>,
Christophe Leroy <christophe.leroy@csgroup.eu>
Subject: RE: [PATCH 2/4] arm64: implement support for static call trampolines
Date: Sat, 25 Sep 2021 17:46:23 +0000 [thread overview]
Message-ID: <944ef479f1104c4a97d0e3f629a9b765@AcuMS.aculab.com> (raw)
In-Reply-To: <20210921162804.GD35846@C02TD0UTHF1T.local>
From: Mark Rutland
> Sent: 21 September 2021 17:28
>
> On Tue, Sep 21, 2021 at 05:55:11PM +0200, Ard Biesheuvel wrote:
> > On Tue, 21 Sept 2021 at 17:33, Mark Rutland <mark.rutland@arm.com> wrote:
> > >
> > > On Tue, Sep 21, 2021 at 04:44:56PM +0200, Ard Biesheuvel wrote:
> > > > On Tue, 21 Sept 2021 at 09:10, Peter Zijlstra <peterz@infradead.org> wrote:
> > ...
...
> > >
> > > I think so, yes. We can do sligntly better with an inline literal pool
> > > and a PC-relative LDR to fold the ADRP+LDR, e.g.
> > >
> > > .align 3
> > > tramp:
> > > BTI C
> > > {B <func> | RET | NOP}
> > > LDR X16, 1f
> > > BR X16
> > > 1: .quad <literal>
> > >
> > > Since that's in the .text, it's RO for regular accesses anyway.
> > >
> >
> > I tried to keep the literal in .rodata to avoid inadvertent gadgets
> > and/or anticipate exec-only mappings of .text, but that may be a bit
> > overzealous.
>
> I think that in practice the risk of gadgetisation is minimal, and
> having it inline means we only need to record a single address per
> trampoline, so there's less risk that we get the patching wrong.
But doesn't that mean that it is almost certainly a data cache miss?
You really want an instruction that reads the constant from the I-cache.
Or at least be able to 'bunch together' the constants so they
stand a chance of sharing a D-cache line.
David
-
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Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2021-09-25 17:46 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 23:32 [PATCH 0/4] arm64: Support dynamic preemption Frederic Weisbecker
2021-09-20 23:32 ` [PATCH 1/4] sched/preempt: Prepare for supporting !CONFIG_GENERIC_ENTRY " Frederic Weisbecker
2021-09-21 7:10 ` Peter Zijlstra
2021-09-21 13:50 ` Mark Rutland
2021-09-20 23:32 ` [PATCH 2/4] arm64: implement support for static call trampolines Frederic Weisbecker
2021-09-21 7:09 ` Peter Zijlstra
2021-09-21 14:44 ` Ard Biesheuvel
2021-09-21 15:08 ` Peter Zijlstra
2021-09-21 15:33 ` Mark Rutland
2021-09-21 15:55 ` Ard Biesheuvel
2021-09-21 16:28 ` Mark Rutland
2021-09-25 17:46 ` David Laight [this message]
2021-09-27 8:58 ` Mark Rutland
2021-09-21 16:10 ` Ard Biesheuvel
2021-09-20 23:32 ` [PATCH 3/4] arm64: Implement IRQ exit preemption static call for dynamic preemption Frederic Weisbecker
2021-09-20 23:32 ` [PATCH 4/4] arm64: Implement HAVE_PREEMPT_DYNAMIC Frederic Weisbecker
2021-10-25 12:20 [PATCH 0/4] arm64: Support dynamic preemption v2 Frederic Weisbecker
2021-10-25 12:21 ` [PATCH 2/4] arm64: implement support for static call trampolines Frederic Weisbecker
2021-10-25 13:56 ` Peter Zijlstra
2021-10-25 14:08 ` Ard Biesheuvel
2021-10-25 14:19 ` Peter Zijlstra
2021-10-25 14:44 ` Peter Zijlstra
2021-10-25 14:55 ` Ard Biesheuvel
2021-10-25 15:03 ` Peter Zijlstra
2021-10-25 15:10 ` Ard Biesheuvel
2021-10-26 10:36 ` Mark Rutland
2021-10-26 10:45 ` Peter Zijlstra
2021-10-26 11:06 ` David Laight
2021-10-27 12:47 ` Mark Rutland
2021-10-25 15:03 ` David Laight
2021-10-25 14:25 ` David Laight
2021-10-25 14:31 ` Ard Biesheuvel
2021-10-25 14:38 ` David Laight
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