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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34f5fb64b3esm1298770a91.10.2026.01.05.23.15.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Jan 2026 23:15:41 -0800 (PST) Message-ID: <9464872c-fd87-42fe-bcc6-1b87a0b21843@oss.qualcomm.com> Date: Tue, 6 Jan 2026 15:15:35 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 0/8] coresight: ctcu: Enable byte-cntr function for TMC ETR To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Mao Jinlong , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski References: <20251224-enable-byte-cntr-for-ctcu-v9-0-886c4496fed4@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20251224-enable-byte-cntr-for-ctcu-v9-0-886c4496fed4@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDA2MCBTYWx0ZWRfX827Sd3Crgfq1 R8euuVdMm2Nd5/G03sBshS/fmzQQ5dmSlvMkBp/h55AuzctzDHlNDggqdJZTWHPyPWKvpBOkCF+ Yyvnr9d2B3/aCkwm5Bsfd09Ells7lRq4Elt9KLx+tecc80n03cJvPGs0tGzLNBNRuFbXYFGFuHf sY9/XFnhr7lJo2VnBRA7TC76pCey7VcUx0nioVGpUfvKY1xL247rzFlPOWW3aqKpzLlVjGJZYlP JiqYQzKvl/zbYmmJmr8Pt/ztNI3Y/1NbaGUHyhKyZ+aiyjEVzdw17FVAeDUmZQ+Y7HXSjwwUaqq JD2D1vv76Y6YIt1dEQxhJYsRrbVqjKljYiJs2DO3aSmTjhzLrVPzvMSG2Fx/FI2GQiOIQ7+6zJI bLcgq5xsQ3rYT5OSMC9kbHzr1A/0Fmr3BxiNChu1Ml9hRPlff4JRPewfEDS9tBHvF08l+4xQpnt ANWHM2po0tJ5rScMRzA== X-Authority-Analysis: v=2.4 cv=Rfidyltv c=1 sm=1 tr=0 ts=695cb6a0 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=hyi39RYjpJE5wifr7rwA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: o41ZRgmdfa_v4vu2JQvknGnxsZESvkuN X-Proofpoint-ORIG-GUID: o41ZRgmdfa_v4vu2JQvknGnxsZESvkuN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 adultscore=0 bulkscore=0 spamscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601060060 On 12/24/2025 5:06 PM, Jie Gan wrote: > The byte-cntr function provided by the CTCU device is used to count the > trace data entering the ETR. An interrupt is triggered if the data size > exceeds the threshold set in the BYTECNTRVAL register. The interrupt > handler counts the number of triggered interruptions. > > Based on this concept, the irq_cnt can be used to determine whether > the etr_buf is full. The ETR device will be disabled when the active > etr_buf is nearly full or a timeout occurs. The nearly full buffer will > be switched to background after synced. A new buffer will be picked from > the etr_buf_list, then restart the ETR device. > > The byte-cntr reading functions can access data from the synced and > deactivated buffer, transferring trace data from the etr_buf to userspace > without stopping the ETR device. > > The byte-cntr read operation has integrated with the file node tmc_etr, > for example: > /dev/tmc_etr0 > /dev/tmc_etr1 > > There are two scenarios for the tmc_etr file node with byte-cntr function: > 1. BYTECNTRVAL register is configured and byte-cntr is enabled -> byte-cntr read > 2. BYTECNTRVAL register is reset or byte-cntr is disabled -> original behavior > > Shell commands to enable byte-cntr reading for etr0: > echo 0x10000 > /sys/bus/coresight/devices/ctcu0/irq_threshold0 > echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink > echo 1 > /sys/bus/coresight/devices/etm0/enable_source > cat /dev/tmc_etr0 > > Reset the BYTECNTR register for etr0: > echo 0 > /sys/bus/coresight/devices/ctcu0/irq_threshold0 > > Changes in v9: > 1. Drop the patch: add a new API to retrieve the helper device > 2. Add a new patch to refactor the tmc_etr_get_catu_device function, > making it generic to support all types of helper devices associated with ETR. > 3. Optimizing the code for creating irq_threshold sysfs node. > Link to v8: https://lore.kernel.org/r/20251211-enable-byte-cntr-for-ctcu-v8-0-3e12ff313191@oss.qualcomm.com > Gentle reminder. > Changes in V8: > 1. Optimizing the patch 1 and patch 2 according to Suzuki's comments. > 2. Combine the patch 3 and patch 4 together. > 3. Rename the interrupt-name to prevent confusion, for example:etr0->etrirq0. > Link to V7 - https://lore.kernel.org/all/20251013-enable-byte-cntr-for-ctcu-v7-0-e1e8f41e15dd@oss.qualcomm.com/ > > Changes in V7: > 1. rebased on tag next-20251010 > 2. updated info for sysfs node document > Link to V6 - https://lore.kernel.org/all/20250908-enable-byte-cntr-for-tmc-v6-0-1db9e621441a@oss.qualcomm.com/ > > Changes in V6: > 1. rebased on next-20250905. > 2. fixed the issue that the dtsi file has re-named from sa8775p.dtsi to > lemans.dtsi. > 3. fixed some minor issues about comments. > Link to V5 - https://lore.kernel.org/all/20250812083731.549-1-jie.gan@oss.qualcomm.com/ > > Changes in V5: > 1. Add Mike's reviewed-by tag for patchset 1,2,5. > 2. Remove the function pointer added to helper_ops according to Mike's > comment, it also results the patchset has been removed. > 3. Optimizing the paired create/clean functions for etr_buf_list. > 4. Remove the unneeded parameter "reading" from the etr_buf_node. > Link to V4 - https://lore.kernel.org/all/20250725100806.1157-1-jie.gan@oss.qualcomm.com/ > > Changes in V4: > 1. Rename the function to coresight_get_in_port_dest regarding to Mike's > comment (patch 1/10). > 2. Add lock to protect the connections regarding to Mike's comment > (patch 2/10). > 3. Move all byte-cntr functions to coresight-ctcu-byte-cntr file. > 4. Add tmc_read_ops to wrap all read operations for TMC device. > 5. Add a function in helper_ops to check whether the byte-cntr is > enabkled. > 6. Call byte-cntr's read_ops if byte-cntr is enabled when reading data > from the sysfs node. > Link to V3 resend - https://lore.kernel.org/all/20250714063109.591-1-jie.gan@oss.qualcomm.com/ > > Changes in V3 resend: > 1. rebased on next-20250711. > Link to V3 - https://lore.kernel.org/all/20250624060438.7469-1-jie.gan@oss.qualcomm.com/ > > Changes in V3: > 1. The previous solution has been deprecated. > 2. Add a etr_buf_list to manage allcated etr buffers. > 3. Add a logic to switch buffer for ETR. > 4. Add read functions to read trace data from synced etr buffer. > Link to V2 - https://lore.kernel.org/all/20250410013330.3609482-1-jie.gan@oss.qualcomm.com/ > > Changes in V2: > 1. Removed the independent file node /dev/byte_cntr. > 2. Integrated the byte-cntr's file operations with current ETR file > node. > 3. Optimized the driver code of the CTCU that associated with byte-cntr. > 4. Add kernel document for the export API tmc_etr_get_rwp_offset. > 5. Optimized the way to read the rwp_offset according to Mike's > suggestion. > 6. Removed the dependency of the dts patch. > Link to V1 - https://lore.kernel.org/all/20250310090407.2069489-1-quic_jiegan@quicinc.com/ > > Signed-off-by: Jie Gan > --- > Jie Gan (8): > coresight: core: Refactoring ctcu_get_active_port and make it generic > coresight: tmc: add create/clean functions for etr_buf_list > coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations > coresight: etr: refactor the tmc_etr_get_catu_device function > dt-bindings: arm: add an interrupt property for Coresight CTCU > coresight: ctcu: enable byte-cntr for TMC ETR devices > coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops > arm64: dts: qcom: lemans: add interrupts to CTCU device > > .../ABI/testing/sysfs-bus-coresight-devices-ctcu | 8 + > .../bindings/arm/qcom,coresight-ctcu.yaml | 10 + > arch/arm64/boot/dts/qcom/lemans.dtsi | 3 + > drivers/hwtracing/coresight/Makefile | 2 +- > drivers/hwtracing/coresight/coresight-catu.c | 3 +- > drivers/hwtracing/coresight/coresight-core.c | 24 ++ > .../hwtracing/coresight/coresight-ctcu-byte-cntr.c | 366 +++++++++++++++++++++ > drivers/hwtracing/coresight/coresight-ctcu-core.c | 122 +++++-- > drivers/hwtracing/coresight/coresight-ctcu.h | 77 ++++- > drivers/hwtracing/coresight/coresight-priv.h | 2 + > drivers/hwtracing/coresight/coresight-tmc-core.c | 104 ++++-- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 144 +++++++- > drivers/hwtracing/coresight/coresight-tmc.h | 40 ++- > 13 files changed, 833 insertions(+), 72 deletions(-) > --- > base-commit: 47b7b5e32bb7264b51b89186043e1ada4090b558 > change-id: 20251203-enable-byte-cntr-for-ctcu-5a4b88f2feb9 > > Best regards,