From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3773CE71D41 for ; Fri, 29 Sep 2023 14:44:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233160AbjI2OoF (ORCPT ); Fri, 29 Sep 2023 10:44:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233601AbjI2Onu (ORCPT ); Fri, 29 Sep 2023 10:43:50 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F3F6CCA for ; Fri, 29 Sep 2023 07:43:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695998625; x=1727534625; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=fQVU2zs87LgiDQcWBNsKywgW89z4peDzqd41cq2SI/g=; b=JYoKIPWmYTuENyQpzBW1aKt39OHR2OhI8aY9BH8QJJMSUt6VVO+BiGVe Xx3rr28b2RlImXrsrNzlplehKBgPHEbj7SfH4Brpfult9UfY13pzAU+vR XZHjHBrwJxsaz+lyvc8k/7klqAx2paSQz7y9mUTwIza7u/5muTmyNzE/b apE7r9xfjMUFVBTpct0+J6Phgii3iok3EMho/wZVmGcoMDkmSInUAJCsd Lijjkr0UXVwTcS2iI1Qn5Op3mbmBBxkH8umHBw3XjlGHKvk4ingG/QyMT XQWFm00IenuGblBni1VwSOQ9aqhZeCW/D26/2w6DTDx+Ar4WnD7xYj9Fo w==; X-IronPort-AV: E=McAfee;i="6600,9927,10848"; a="386177695" X-IronPort-AV: E=Sophos;i="6.03,187,1694761200"; d="scan'208";a="386177695" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 07:43:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10848"; a="873703208" X-IronPort-AV: E=Sophos;i="6.03,187,1694761200"; d="scan'208";a="873703208" Received: from smorozov-mobl1.ger.corp.intel.com ([10.252.52.167]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2023 07:43:41 -0700 Date: Fri, 29 Sep 2023 17:43:39 +0300 (EEST) From: =?ISO-8859-15?Q?Ilpo_J=E4rvinen?= To: Maciej Wieczor-Retman cc: Fenghua Yu , Reinette Chatre , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Peter Newman , LKML Subject: Re: [PATCH v3 2/4] x86/resctrl: Enable non-contiguous CBMs in Intel CAT In-Reply-To: <54256710ab7f83bf5fd43c644c0a97b728b8f0b7.1695977733.git.maciej.wieczor-retman@intel.com> Message-ID: <94677dc2-4d17-6e7b-dda2-c14371a48d47@linux.intel.com> References: <54256710ab7f83bf5fd43c644c0a97b728b8f0b7.1695977733.git.maciej.wieczor-retman@intel.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-541821045-1695998624=:1989" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-541821045-1695998624=:1989 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8BIT On Fri, 29 Sep 2023, Maciej Wieczor-Retman wrote: > The setting for non-contiguous 1s support in Intel CAT is > hardcoded to false. On these systems, writing non-contiguous > 1s into the schemata file will fail before resctrl passes > the value to the hardware. > > In Intel CAT CPUID.0x10.1:ECX[3] and CPUID.0x10.2:ECX[3] stopped > being reserved and now carry information about non-contiguous 1s > value support for L3 and L2 cache respectively. The CAT > capacity bitmask (CBM) supports a non-contiguous 1s value if > the bit is set. > > Replace the hardcoded non-contiguous support value with > the support learned from the hardware. Add hardcoded non-contiguous > support value to Haswell probe since it can't make use of CPUID for > Cache allocation. > > Originally-by: Fenghua Yu > Reviewed-by: Peter Newman > Tested-by: Peter Newman > Signed-off-by: Maciej Wieczor-Retman > --- > Changelog v3: > - Add Peter's tested-by and reviewed-by tags. > - Change patch subject to mention CBMs. (Babu) > > Changelog v2: > - Rewrite part of a comment concerning Haswell. (Reinette) > > arch/x86/kernel/cpu/resctrl/core.c | 9 ++++++--- > arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 10 ++++++---- > arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++ > 3 files changed, 21 insertions(+), 7 deletions(-) > > diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c > index c09e4fdded3c..19e0681f0435 100644 > --- a/arch/x86/kernel/cpu/resctrl/core.c > +++ b/arch/x86/kernel/cpu/resctrl/core.c > @@ -152,6 +152,7 @@ static inline void cache_alloc_hsw_probe(void) > r->cache.cbm_len = 20; > r->cache.shareable_bits = 0xc0000; > r->cache.min_cbm_bits = 2; > + r->cache.arch_has_sparse_bitmasks = false; > r->alloc_capable = true; > > rdt_alloc_capable = true; > @@ -267,15 +268,18 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) > { > struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); > union cpuid_0x10_1_eax eax; > + union cpuid_0x10_x_ecx ecx; > union cpuid_0x10_x_edx edx; > - u32 ebx, ecx; > + u32 ebx; > > - cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full); > + cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); > hw_res->num_closid = edx.split.cos_max + 1; > r->cache.cbm_len = eax.split.cbm_len + 1; > r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; > r->cache.shareable_bits = ebx & r->default_ctrl; > r->data_width = (r->cache.cbm_len + 3) / 4; > + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) > + r->cache.arch_has_sparse_bitmasks = ecx.split.noncont; > r->alloc_capable = true; > } > > @@ -872,7 +876,6 @@ static __init void rdt_init_res_defs_intel(void) > > if (r->rid == RDT_RESOURCE_L3 || > r->rid == RDT_RESOURCE_L2) { > - r->cache.arch_has_sparse_bitmasks = false; > r->cache.arch_has_per_cpu_cfg = false; > r->cache.min_cbm_bits = 1; > } else if (r->rid == RDT_RESOURCE_MBA) { > diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c > index ab45012288bb..beccb0e87ba7 100644 > --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c > +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c > @@ -87,10 +87,12 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s, > > /* > * Check whether a cache bit mask is valid. > - * For Intel the SDM says: > - * Please note that all (and only) contiguous '1' combinations > - * are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.). > - * Additionally Haswell requires at least two bits set. > + * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID: > + * - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1 > + * - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1 > + * > + * Haswell does not support a non-contiguous 1s value and additionally > + * requires at least two bits set. > * AMD allows non-contiguous bitmasks. > */ > static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) > diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h > index 85ceaf9a31ac..c47ef2f13e8e 100644 > --- a/arch/x86/kernel/cpu/resctrl/internal.h > +++ b/arch/x86/kernel/cpu/resctrl/internal.h > @@ -492,6 +492,15 @@ union cpuid_0x10_3_eax { > unsigned int full; > }; > > +/* CPUID.(EAX=10H, ECX=ResID).ECX */ > +union cpuid_0x10_x_ecx { > + struct { > + unsigned int reserved:3; > + unsigned int noncont:1; > + } split; > + unsigned int full; > +}; > + > /* CPUID.(EAX=10H, ECX=ResID).EDX */ > union cpuid_0x10_x_edx { > struct { > Reviewed-by: Ilpo Järvinen -- i. --8323329-541821045-1695998624=:1989--