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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI4MDE2NyBTYWx0ZWRfXxG3swkyOApiK f6j5mel6gr3iVgrTZflpGN71oPmyw6cpBA2uLYeM6tOXG1g2Xt6yqt1Bbyr3GNSredLypv5xWBk PqApWRZyrSYFiEMDrwyOXZaItZpLF+QaRhEo/Vb2Ei/vQwyR7shnXJx63/btTRfs/ZPt1CSMi4X 9F4ZgETEPTEWV9VoIcbV7hamop2Q9NZEmiYPe6KKmSxeO7sLN+2u2lOv7H7JSYw5KEkR8JAb+Ea nBYbcdOBNfXF5owwlsyLe86DVGAq+n0tfvtBlB4bdDXKjELiHxTGQk+cz7ASg0pCyFmqNhCW0HY ohDrSZ9TLgVv1tg7c+SkZuQWjyCuAoTmATLvJWJAUeeXqaugf0AqD9hGaBs7fCSeX7oBEQcQL1G lWwWcD9JxNldbaVDRv/o4StouSwJWZ7KLS1sg7Z5Bm98zbF3wcMAfLgitnwOQnZNTsvuxOF5fT6 2rZpZhLuoMhf++6J1YA== X-Authority-Analysis: v=2.4 cv=Uu5T8ewB c=1 sm=1 tr=0 ts=69f0ed91 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=EwI1ikYXukqkrg4G3Narhw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=HjAgAaymx-b2fZWta2cA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: TYsPXeqvh19aG2lb67gyXv9p4o8hBvEb X-Proofpoint-GUID: TYsPXeqvh19aG2lb67gyXv9p4o8hBvEb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 adultscore=0 clxscore=1015 suspectscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280167 On 4/24/2026 2:39 PM, Krzysztof Kozlowski wrote: > On 22/04/2026 09:41, Krzysztof Kozlowski wrote: >> On Mon, Apr 20, 2026 at 09:58:55PM +0530, Jagadeesh Kona wrote: >>> On SM8750, a subset of DISPCC clocks is controlled by the display CESTA >>> (Client State Aggregator) hardware. These clocks can be scaled to the >>> desired frequency by sending votes to the display CRM(CESTA Resource >>> manager) instead of programming DISPCC registers directly. >> >> This looks like completely new, vendor clock API, so no. >> >> Resource voting or clock scaling is nothing new and you do not get a >> vendor phandle to do it. That's like basic upstreaming 101: we do not >> want another vendor re-implementation of common or typical solutions. > > I'll provide a bit more context, what I am looking for: > Are CESTA and CRMC truly separate blocks? Do they have their own > resources or maybe something is shared with clock controller, e.g. parts > of address space? > Thanks Krzysztof for your review CRMC is sub-block within the CESTA block. CRMC block contains the clocks frequency lookup tables information for CESTA controlled RCGs, which clock driver needs to read and populate the RCG's frequency tables. DISPCC block is outside of CESTA block, so CRMC block is mapped as syscon device and is used in DISPCC node only to read & populate the CESTA controlled RCGs frequency lookup tables. The actual clock scaling is done later by converting the frequency into a perf level & sending it to CESTA HW via CRM APIs. > If they manage clocks, they should receive some of the clocks as inputs, > because I don't imagine a block which gates clock somewhere else, to > which it has no access (IOW, that gate to manage clock is part of the > clock). Or maybe it's some shadow registers? Or display clock controller > does not have direct clock access in the first place? > Yes, there are few dispcc clocks required for accessing the display CRM/CRMC register blocks but those clocks are already kept ON from bootloader and they will stay ON as long as MMCX rail is voted. So if MMCX is ON, we can access CRM/CRMC blocks. Thanks, Jagadeesh