From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C00F9CCA47F for ; Mon, 20 Jun 2022 03:29:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237897AbiFTD3k (ORCPT ); Sun, 19 Jun 2022 23:29:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237878AbiFTD3j (ORCPT ); Sun, 19 Jun 2022 23:29:39 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4D876249; Sun, 19 Jun 2022 20:29:37 -0700 (PDT) X-UUID: 6044d4ae9b2a415eade352b1ed265ef6-20220620 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:8e2cf951-ce8b-47aa-b497-87933e53de16,OB:10,L OB:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,AC TION:release,TS:45 X-CID-INFO: VERSION:1.1.6,REQID:8e2cf951-ce8b-47aa-b497-87933e53de16,OB:10,LOB :0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:45 X-CID-META: VersionHash:b14ad71,CLOUDID:6939f5e9-f7af-4e69-92ee-0fd74a0c286c,C OID:3cc8a5dd8204,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: 6044d4ae9b2a415eade352b1ed265ef6-20220620 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1014500687; Mon, 20 Jun 2022 11:29:27 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 20 Jun 2022 11:29:26 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 20 Jun 2022 11:29:26 +0800 Message-ID: <94b03604c81794ea811e106802a03b888ceb57c3.camel@mediatek.com> Subject: Re: [PATCH v11 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver From: CK Hu To: Bo-Chen Chen , , , , , , , , , , CC: , , , , , , , , , , , Date: Mon, 20 Jun 2022 11:29:25 +0800 In-Reply-To: <20220610105522.13449-6-rex-bc.chen@mediatek.com> References: <20220610105522.13449-1-rex-bc.chen@mediatek.com> <20220610105522.13449-6-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Rex: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen > --- [snip] > + > +static void mtk_dp_set_color_depth(struct mtk_dp *mtk_dp, u32 > color_depth) In the whole driver, the color_depth would only be DP_MSA_MISC_8_BPC, so remove the parameter color_depth and fix the color depth to DP_MSA_MISC_8_BPC in this function. Regards, CK > +{ > + u32 val; > + > + mtk_dp->info.depth = color_depth; > + > + /* Update MISC0 */ > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034, > + color_depth, DP_TEST_BIT_DEPTH_MASK); > + > + switch (color_depth) { > + case DP_MSA_MISC_6_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT; > + break; > + case DP_MSA_MISC_8_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT; > + break; > + case DP_MSA_MISC_10_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT; > + break; > + case DP_MSA_MISC_12_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT; > + break; > + case DP_MSA_MISC_16_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT; > + break; > + default: > + drm_warn(mtk_dp->drm_dev, "Unsupported color depth > %d\n", > + color_depth); > + return; > + } > + > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C, val, > + VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK); > +} > +