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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3142a1de21asm47287844eec.23.2026.07.21.04.11.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jul 2026 04:12:00 -0700 (PDT) Message-ID: <94b10cea-7541-43e7-bdca-ab79e5729d55@oss.qualcomm.com> Date: Tue, 21 Jul 2026 04:11:59 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] dmaengine: qcom: gpi: Fix SE ID and SE Protocol fields widths in SCRATCH_0 To: Konrad Dybcio , Vinod Koul , Frank Li , bjorn.andersson@oss.qualcomm.com Cc: praveen.talari@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, mukesh.savaliya@oss.qualcomm.com References: <20260720-fix_se_id_and_se_protocol_fields-v1-1-e41dbb107d97@oss.qualcomm.com> <34b0bb3b-d756-4cd6-806d-75b1124f4397@oss.qualcomm.com> Content-Language: en-US From: Chandana Kishori Chiluveru In-Reply-To: <34b0bb3b-d756-4cd6-806d-75b1124f4397@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: niudKtIAFlueuYS5Z7LxHGQIh3BmGvng X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDExOCBTYWx0ZWRfX8geKzRXOsRd2 feGkoptB2iva1KVINO1BaTE+/CqY2BH24JPRDLqsotATQ78EE0SCc4uzs1NX/6KbTzsc/TH2aVq XeVC5D3qcDpXYuD7a1FIhVgW8hRSLEN4QMALz1B7rc/6b1qNjqC0yU9BfKdehrhkJ8HYA/P4yH/ avSOvAlGPIBUZFKeHFQscG9N2prtnLC2I0hO7Ix/EkMoAH2fU1yh/7oxOYeAqedj8b+/z2zqL9J WR441YdbXbO15QcfvU8bwV/g/K9to7qBomKq03u9xTGk9iAS42fMLBzV27GgOybwXBSv4nlOORT WZAUZ9YlH0kW1PmaAQbw15XSenPoHWK/147SuPgJVx8cKieF2DNPtIsbEx7nzTPBZh4owGjZw41 hAMDP4Py1i2pHO37UyoJeGx0Q04qK/5TK5fiV72qjoIkSxdPNfZo/eALgRbaRa8OHe+K9LjP8j3 Git2cBOdfiWwVLSDG5w== X-Authority-Analysis: v=2.4 cv=I9JVgtgg c=1 sm=1 tr=0 ts=6a5f5402 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=-nvh27Yv-2H1FMEgutIA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: niudKtIAFlueuYS5Z7LxHGQIh3BmGvng X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDExOCBTYWx0ZWRfXwNbqNzW2ZKlq KlUrVW1vuwjOWNCgGJyHUo3vQ7nDskd6Q3e8uflCSr6Zu+5jpoZ9VHgoHmiPvf7U+98BNRfuCZK H4vtn/hBAzfXEbLH/LesG3olWApcJ+c= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-21_01,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210118 HI Konrad On 7/20/26 08:47, Konrad Dybcio wrote: > On 7/20/26 5:27 PM, Chandana Kishori Chiluveru wrote: >> GPII_n_CH_k_SCRATCH_0_SEID is currently defined as GENMASK(2, 0), only >> 3 bits wide. Serial engine indices >= 8 get silently truncated by >> FIELD_PREP()/u32_encode_bits() when written into the scratch register, >> causing the GPI channel to bind to the wrong serial engine. The >> channel allocate command still succeeds (it doesn't require the >> target SE to respond), but the subsequent channel start command times >> out waiting for hardware to complete the handoff to the (incorrectly >> bound) SE, and gpi_send_cmd() returns -EIO leading to GSI usecase failures >> for SE8 and SE9 serial engines. >> >> Older documentation, such as the SDM845 hardware programming guide, >> describes the SE ID field as bits [2:0]. More recent QUP hardware >> documentation defines the field as bits [3:0]. Use the wider definition >> to match current hardware documentation while remaining compatible with >> existing platforms and enabling serial engine IDs greater than 7. >> >> Also update the SE Protocol field definition to match the documented >> register layout and keep both fields correctly packed. >> >> Fixes: 5d0c3533a19f ("dmaengine: qcom: Add GPI dma driver") >> Signed-off-by: Chandana Kishori Chiluveru >> --- >> drivers/dma/qcom/gpi.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c >> index a5055a6273af..8f09eaf4e714 100644 >> --- a/drivers/dma/qcom/gpi.c >> +++ b/drivers/dma/qcom/gpi.c >> @@ -207,8 +207,8 @@ enum CNTXT_OFFS { >> >> /* Scratch registers */ >> #define GPII_n_CH_k_SCRATCH_0_OFFS(n, k) (0x20060 + (0x4000 * (n)) + (0x80 * (k))) >> -#define GPII_n_CH_k_SCRATCH_0_SEID GENMASK(2, 0) >> -#define GPII_n_CH_k_SCRATCH_0_PROTO GENMASK(7, 4) >> +#define GPII_n_CH_k_SCRATCH_0_SEID GENMASK(3, 0) >> +#define GPII_n_CH_k_SCRATCH_0_PROTO GENMASK(6, 4) > There exist protocols, such as QSPI with id=9, so this surely can't Its my bad, The PROTO field should be [8:4]. I will correct this in the next patch > be right (unless there's another bitfield for that?) > > Konrad >