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[93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493c6375764sm314379715e9.5.2026.07.06.02.35.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Jul 2026 02:35:03 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 11/15] arm64: dts: imx8mn-var-som-symphony: Enable I2C4 Date: Mon, 6 Jul 2026 11:34:41 +0200 Message-ID: <94b2e50c4f11be384161eb8fdfc82a5c1d7ebc4c.1783330236.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli Enable I2C4 on the Symphony carrier and add pinctrl configuration, including GPIO-based bus recovery support. Signed-off-by: Stefano Radaelli --- v1->v2: - .../dts/freescale/imx8mn-var-som-symphony.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 7d016ed5e911..4898018f030c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -195,6 +195,16 @@ rtc@68 { }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; @@ -262,6 +272,20 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 -- 2.47.3