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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id s16-20020ac25ff0000000b004cb3e97bff8sm757705lfg.284.2023.02.26.19.09.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 26 Feb 2023 19:09:28 -0800 (PST) Message-ID: <94c18cc3-4b1a-440b-3bd8-3c81ddffc148@linaro.org> Date: Mon, 27 Feb 2023 05:09:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [PATCH v10 4/6] soc: qcom: cpr: Move common functions to new file Content-Language: en-GB To: Konrad Dybcio , AngeloGioacchino Del Regno , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Viresh Kumar , Nishanth Menon , Stephen Boyd , Niklas Cassel , Liam Girdwood , Mark Brown Cc: Robert Marko , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, AngeloGioacchino Del Regno References: <20230217-topic-cpr3h-v10-0-67aed8fdfa61@linaro.org> <20230217-topic-cpr3h-v10-4-67aed8fdfa61@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20230217-topic-cpr3h-v10-4-67aed8fdfa61@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/02/2023 13:08, Konrad Dybcio wrote: > From: AngeloGioacchino Del Regno > > In preparation for implementing a new driver that will be handling > CPRv3, CPRv4 and CPR-Hardened, format out common functions to a new > file. > > Update cpr_get_fuses in preparation for CPR3 implementation, change > parameters where necessary to not take cpr.c private data structures. > > Signed-off-by: AngeloGioacchino Del Regno > [Konrad: rebase, apply review comments, don't break backwards compat, improve msg] > Signed-off-by: Konrad Dybcio > --- > drivers/soc/qcom/Makefile | 2 +- > drivers/soc/qcom/cpr-common.c | 363 +++++++++++++++++++++++++++++++++++++++ > drivers/soc/qcom/cpr-common.h | 108 ++++++++++++ > drivers/soc/qcom/cpr.c | 386 +++--------------------------------------- > 4 files changed, 494 insertions(+), 365 deletions(-) > [skipped] > diff --git a/drivers/soc/qcom/cpr-common.h b/drivers/soc/qcom/cpr-common.h > new file mode 100644 > index 000000000000..2cd15f7eac90 > --- /dev/null > +++ b/drivers/soc/qcom/cpr-common.h > @@ -0,0 +1,108 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > + > +#include > +#include > +#include > +#include > + > +enum voltage_change_dir { > + NO_CHANGE, > + DOWN, > + UP, > +}; > + > +struct fuse_corner_data { > + int ref_uV; > + int max_uV; > + int min_uV; > + int range_uV; > + /* fuse volt: closed/open loop */ > + int volt_cloop_adjust; > + int volt_oloop_adjust; For CPR3 these values are per-fusing-rev. (for 8996 tables list per-fusing-rev values for min_uV, volt_cloop_adjust and volt_oloop_adjust) Another option, of course, might be to have a per-SoC code that uses fusing_rev to update the fuse_corner_data, but it would mean making it non-const. > + int max_volt_scale; > + int max_quot_scale; Any reason for these limitations? > + /* fuse quot */ > + int quot_offset; > + int quot_scale; > + int quot_adjust; I see that quot_offset/quot_scale/quot_adjust are set to 0/1/0 for all the platforms I can assess at this moment (8996/8998/sdm660). Can we drop them? If we need them later, we can readd them later. > + /* fuse quot_offset */ > + int quot_offset_scale; > + int quot_offset_adjust; > +}; > + > +struct cpr_fuse { > + char *ring_osc; > + char *init_voltage; > + char *quotient; > + char *quotient_offset; > +}; > + > +struct fuse_corner { > + int min_uV; > + int max_uV; > + int uV; > + int quot; > + int step_quot; > + const struct reg_sequence *accs; > + int num_accs; > + unsigned long max_freq; > + u8 ring_osc_idx; > +}; > + > +struct corner { > + int min_uV; > + int max_uV; > + int uV; > + int last_uV; > + int quot_adjust; > + u32 save_ctl; > + u32 save_irq; > + unsigned long freq; > + bool is_open_loop; > + struct fuse_corner *fuse_corner; > +}; > + > +struct corner_data { > + unsigned int fuse_corner; > + unsigned long freq; > +}; > + > +struct acc_desc { > + unsigned int enable_reg; > + u32 enable_mask; > + > + struct reg_sequence *config; > + struct reg_sequence *settings; > + int num_regs_per_fuse; > +}; > + > +struct cpr_acc_desc { > + const struct cpr_desc *cpr_desc; > + const struct acc_desc *acc_desc; > +}; > + [skipped the rest] -- With best wishes Dmitry