Re: [PATCH v2] cxl/port: Fix endpoint RAS error unmasking

["Cheatham, Benjamin" <benjamin.cheatham@amd.com>]

On 11/3/2026 5:15 PM, Dave Jiang wrote:
> 
> 
> On 11/3/26 11:35 AM, Cheatham, Benjamin wrote:
>> On 11/3/2026 12:34 AM, Richard Cheng wrote:
>>> Moving endpoint RAS handling from cxl_pci to cxl_port left
>>> cxl_ras_unmask() checking whether port->uport_dev is a PCI device.
>>> Endpoint ports always use a cxl_memdev as uport_dev, so this check
>>> returns early and leaves the CXL RAS error masks unchanged.
>>>
>>> Resolve the PCI device directly through the memdev's parent. Rename
>>> helper to cxl_endpoint_ras_unmask() and its param to endpoint to make
>>> its endpoint-only scope explicit.
>>>
>>> Fixes: dab7162d0ae7 ("cxl/port: Move endpoint component register management to cxl_port")
>>> Signed-off-by: Richard Cheng <icheng@nvidia.com>
>>> ---
>>
>> ...
>>
>>> -static int cxl_ras_unmask(struct cxl_port *port)
>>> +static int cxl_endpoint_ras_unmask(struct cxl_port *endpoint)
>>>  {
>>> +	struct cxl_memdev *cxlmd = to_cxl_memdev(endpoint->uport_dev);
>>> +	struct device *parent = cxlmd->dev.parent;
>>
>> Two small nits:
>>
>> 1. Maybe just use endpoint->uport_dev.parent directly and drop the cxlmd part? It's less
>> readable, but it's future proofing for when/if CXL.cache devices come along.
>>
>> 2. I don't think you need to rename the port parameter if you change the name to endpoint. It's
>> self-explanatory at that point and cuts down on the diff.
> 
> I asked for that change. Since we are making changes on that line already, may as well make it explicit for readability. Or at least satisfies my OCD :)
> 
> DJ
> 

Ahh ok, then that's fine with me.

Thanks,
Ben