From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754178AbdHWPNH (ORCPT ); Wed, 23 Aug 2017 11:13:07 -0400 Received: from hermes.aosc.io ([199.195.250.187]:49715 "EHLO hermes.aosc.io" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754090AbdHWPNG (ORCPT ); Wed, 23 Aug 2017 11:13:06 -0400 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Date: Wed, 23 Aug 2017 23:13:04 +0800 From: icenowy@aosc.io To: Maxime Ripard Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 In-Reply-To: <20170823143532.owocqyq3tehsahhg@flea.home> References: <20170822061742.40869-1-icenowy@aosc.io> <20170822200521.nadkb4335mcc5ah2@flea.home> <20170823143532.owocqyq3tehsahhg@flea.home> Message-ID: <9554c7524c8608e1eceafe762a487c11@aosc.io> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2017-08-23 22:35，Maxime Ripard 写道： > On Wed, Aug 23, 2017 at 07:56:29PM +0800, icenowy@aosc.io wrote: >> > > + reg = <0x01c0f000 0x1000>; >> > > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; >> > > + clock-names = "ahb", "mmc"; >> > > + resets = <&ccu RST_BUS_MMC0>; >> > > + reset-names = "ahb"; >> > > + pinctrl-0 = <&mmc0_pins>; >> > > + pinctrl-names = "default"; >> > > + interrupts = ; >> > > + max-frequency = <150000000>; >> > >> > have you tested that frequency? >> >> I think the frequency should be kept here, although my cards cannot >> reach this frequency. >> >> The numbers are same as the corresponding controllers in A64. >> >> Maybe I should add a comment saying it's educated guess? > > I'd rather have it tested by someone, and then add the proper > frequencies. It took quite a while to figure out how these modes were > supposed to be working on the A64, so it's not obvious that they're > just going to work. Should I add my results here? MMC0: 25MHz MMC1: 50MHz MMC2: 52MHz MMC3: not wired :-( I think it's conservative enough and works well ;-) > >> > > + gic: interrupt-controller@1c81000 { >> > > + compatible = "arm,gic-400"; >> > > + reg = <0x01c81000 0x1000>, >> > > + <0x01c82000 0x1000>, >> > > + <0x01c84000 0x2000>, >> > > + <0x01c86000 0x2000>; >> > > + interrupt-controller; >> > > + #interrupt-cells = <3>; >> > > + interrupts = > > > IRQ_TYPE_LEVEL_HIGH)>; >> > > + }; >> > > + }; >> > > + >> > > + timer { >> > > + compatible = "arm,armv7-timer"; >> > > + interrupts = > > > IRQ_TYPE_LEVEL_LOW)>, >> > > + , >> > > + , >> > > + ; >> > >> > Those masks are wrong. >> >> I compared it with other sun8i SoCs' device tree. >> >> Where's wrong? > > It's supposed to be a mask of the CPUs in your system. Since you just > have one of them, it shouldn't be 4. R40 has 4 cores... Or I didn't understand this? > > Maxime