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Tue, 25 Aug 2026 01:19:31 -0700 (PDT) X-Received: by 2002:a05:6a00:1ca8:b0:84c:1cd2:142b with SMTP id d2e1a72fcca58-8523c8f0862mr9113505b3a.9.1787645970964; Tue, 25 Aug 2026 01:19:30 -0700 (PDT) Received: from [10.218.14.97] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8520f161701sm2725924b3a.53.2026.08.25.01.19.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Aug 2026 01:19:30 -0700 (PDT) Message-ID: <956ad5fd-7710-4731-9796-b03dc21cb2a4@oss.qualcomm.com> Date: Tue, 25 Aug 2026 13:49:23 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] i2c: qcom-geni: Use geni_se_set_rate() for setting source clock frequency To: Konrad Dybcio , Sudeep Holla , Cristian Marussi , Ulf Hansson , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Jiri Slaby , Mark Brown , Viken Dadhaniya , Andi Shyti Cc: mukesh.savaliya@oss.qualcomm.com, chandana.chiluveru@oss.qualcomm.com, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-0-61171ab1cdce@oss.qualcomm.com> <20260805-derive_clk_perf_tbl_from_perf_domain_opp_table-v1-7-61171ab1cdce@oss.qualcomm.com> Content-Language: en-US From: Praveen Talari In-Reply-To: Content-Type: text/plain; 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On 24-08-2026 20:36, Konrad Dybcio wrote: > On 8/4/26 9:57 PM, Praveen Talari wrote: >> On the SA8255P platform there is no Linux clock handler for the SE source >> clock; resources are instead managed by firmware via a genpd performance >> domain. The I2C driver therefore relies on geni_se_set_rate() to apply the >> fixed 19.2 MHz source clock frequency expected by the SCL divider and >> counter values programmed by qcom_geni_i2c_conf(). > [...] > >> @@ -233,6 +233,10 @@ static int qcom_geni_i2c_conf(struct geni_se *se, unsigned long freq) >> itr->clk_div, itr->t_high_cnt, >> itr->t_low_cnt, itr->t_cycle_cnt); >> >> + ret = geni_se_set_rate(&gi2c->se, 19200000); >> + if (ret) >> + return ret; > This wasn't here before and the commit message only says something to the Yes, it was not there earlier. I have added because of Fast-mode Plus (1 MHz) cannot achieve the required timings with the default 19.2 MHz source clock. A higher source frequency (for example, 32.5 MHz or 37.5 MHz) is required, along with the associated voltage/performance vote. Thanks, Praveen Talari > amount of "it's necessary" - what's the difference? > > Konrad