From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.mindbit.ro (xs1.mindbit.ro [80.86.107.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7001A3F661D for ; Thu, 2 Apr 2026 16:41:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.86.107.70 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775148121; cv=none; b=MilcpfrAXRX7yIBBQtlVp0Lg6DyJXqJu8TKXKx5M4LIWXb1zC9hKhvzsthoJOt4nlLVs/6pofLa718thWsnxIAH43NK47BNbeVTz3CMy6qqgfwOSAN1csVF3I9cpwexeOEtMgD8OMHnC2Q0x8FqpDQvRPWPWUz66KAnwb9A5L5U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775148121; c=relaxed/simple; bh=aBwj5e9qxwC6mp8jHz94bCBUKZ4EsEAagEs9ZiVmddw=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=tjN/626w2k0AYq/gUL/AaVHvWpVlHnVORy9SeEVMLpYKPyVYAVZQYYOBgaqTMSUuWPnNHVbbpGNmYoKauj0gnLfwDGmbhB+HtpRB1eJOOgyd+oCDiXJAnBu/6E0GEj+6/rgESIIVT99NzJemVWrutwxoabqEwWnZ5y7rUN6pbQY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net; spf=pass smtp.mailfrom=rendec.net; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b=F/wnvo6o; arc=none smtp.client-ip=80.86.107.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=rendec.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rendec.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rendec.net header.i=@rendec.net header.b="F/wnvo6o" Received: from dog.kanata.rendec.net (pool-174-112-193-187.cpe.net.cable.rogers.com [174.112.193.187]) by mail.mindbit.ro (Postfix) with ESMTPSA id 896F0C2540; Thu, 2 Apr 2026 19:41:47 +0300 (EEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.mindbit.ro 896F0C2540 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rendec.net; s=default; t=1775148109; bh=geF+TZUIzvvb3BTfJSJJ7uAgGZs//rbxTgdWVIEjWRQ=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=F/wnvo6o0OJmCTAYGRZJHSUw8F29gNifY9hmG6VbAUmtvi1XYdN4stdHHRZS0SxrL +V25NLiKu6VlAlnG5WjXEMS3yEZoAlA3ddpXU4fdkyIer1IEGKbIvP2dtSixWa4wR6 04Xf6zphMF7oD/72pUCCi0KXEg0xvnQN+d3newHgyr/DN+osGp8xlrroUSTtq9mg+d T2nISCR9lucXxosuBl72fph95Ma5cBvKaTKIInn2y3Fj6+dTNKZnIEdR84sXtJDl+F nVd9QE6ti/HamzgzSIAsqVfG2IH5XIAIvoeNWWXHj82QUvrpp5G9ITXvhyiSlBFVhd n0Q66jh6ADvPg== Message-ID: <958913dba3e734f8e8828e67756b24bccaee55ed.camel@rendec.net> Subject: Re: [patch V5 06/15] x86/irq: Move IOAPIC misrouted and PIC/APIC error counts into irq_stats From: Radu Rendec To: Thomas Gleixner , LKML Cc: x86@kernel.org, Michael Kelley , Dmitry Ilvokhin , Jan Kiszka , Kieran Bingham , Florian Fainelli , Marc Zyngier Date: Thu, 02 Apr 2026 12:41:46 -0400 In-Reply-To: <20260401201348.423288866@kernel.org> References: <20260401195625.213446764@kernel.org> <20260401201348.423288866@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2026-04-01 at 23:52 +0200, Thomas Gleixner wrote: > From: Thomas Gleixner >=20 > The special treatment of these counts is just adding extra code for no re= al > value. The irq_stats mechanism allows to suppress output of counters, whi= ch > should never happen by default and provides a mechanism to enable them fo= r > the rare case that they occur. >=20 > Move the IOAPIC misrouted and the PIC/APIC error counts into irq_stats, > mark them suppressed by default and update the sites which increment them= . >=20 > This changes the output format of 'ERR' and 'MIS' in case there are event= s > to the regular per CPU display format and otherwise suppresses them > completely. >=20 > As a side effect this removes the arch_cpu_stat() mechanism from proc/sta= t > which was only there to account for the error interrupts on x86 and misse= d > to take the misrouted ones into account. >=20 > Signed-off-by: Thomas Gleixner > --- > V3: New patch > --- > =C2=A0arch/x86/include/asm/hardirq.h |=C2=A0=C2=A0=C2=A0 7 ++++--- > =C2=A0arch/x86/include/asm/hw_irq.h=C2=A0 |=C2=A0=C2=A0=C2=A0 4 ---- > =C2=A0arch/x86/kernel/apic/apic.c=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0 2= +- > =C2=A0arch/x86/kernel/apic/io_apic.c |=C2=A0=C2=A0=C2=A0 4 +--- > =C2=A0arch/x86/kernel/i8259.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0=C2=A0=C2=A0 2 +- > =C2=A0arch/x86/kernel/irq.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0 16 ++++------------ > =C2=A0fs/proc/stat.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0 4 ---- > =C2=A07 files changed, 11 insertions(+), 28 deletions(-) > --- a/arch/x86/include/asm/hardirq.h > +++ b/arch/x86/include/asm/hardirq.h > @@ -50,6 +50,10 @@ enum irq_stat_counts { > =C2=A0#ifdef CONFIG_X86_POSTED_MSI > =C2=A0 IRQ_COUNT_POSTED_MSI_NOTIFICATION, > =C2=A0#endif > + IRQ_COUNT_PIC_APIC_ERROR, > +#ifdef CONFIG_X86_IO_APIC > + IRQ_COUNT_IOAPIC_MISROUTED, > +#endif > =C2=A0 IRQ_COUNT_MAX, > =C2=A0}; > =C2=A0 > @@ -81,9 +85,6 @@ extern void ack_bad_irq(unsigned int irq > =C2=A0#ifdef CONFIG_PROC_FS > =C2=A0extern u64 arch_irq_stat_cpu(unsigned int cpu); > =C2=A0#define arch_irq_stat_cpu arch_irq_stat_cpu > - > -extern u64 arch_irq_stat(void); > -#define arch_irq_stat arch_irq_stat > =C2=A0#endif > =C2=A0 > =C2=A0DECLARE_PER_CPU_CACHE_HOT(u16, __softirq_pending); > --- a/arch/x86/include/asm/hw_irq.h > +++ b/arch/x86/include/asm/hw_irq.h > @@ -110,10 +110,6 @@ static inline void lock_vector_lock(void > =C2=A0static inline void unlock_vector_lock(void) {} > =C2=A0#endif > =C2=A0 > -/* Statistics */ > -extern atomic_t irq_err_count; > -extern atomic_t irq_mis_count; > - > =C2=A0extern void elcr_set_level_irq(unsigned int irq); > =C2=A0 > =C2=A0extern char irq_entries_start[]; > --- a/arch/x86/kernel/apic/apic.c > +++ b/arch/x86/kernel/apic/apic.c > @@ -2180,7 +2180,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_error_inte > =C2=A0 apic_write(APIC_ESR, 0); > =C2=A0 v =3D apic_read(APIC_ESR); > =C2=A0 apic_eoi(); > - atomic_inc(&irq_err_count); > + irq_stat_inc_and_enable(IRQ_COUNT_PIC_APIC_ERROR); > =C2=A0 > =C2=A0 apic_pr_debug("APIC error on CPU%d: %02x", smp_processor_id(), v); > =C2=A0 > --- a/arch/x86/kernel/apic/io_apic.c > +++ b/arch/x86/kernel/apic/io_apic.c > @@ -1575,8 +1575,6 @@ static unsigned int startup_ioapic_irq(s > =C2=A0 return was_pending; > =C2=A0} > =C2=A0 > -atomic_t irq_mis_count; > - > =C2=A0#ifdef CONFIG_GENERIC_PENDING_IRQ > =C2=A0static bool io_apic_level_ack_pending(struct mp_chip_data *data) > =C2=A0{ > @@ -1713,7 +1711,7 @@ static void ioapic_ack_level(struct irq_ > =C2=A0 * at the cpu. > =C2=A0 */ > =C2=A0 if (!(v & (1 << (i & 0x1f)))) { > - atomic_inc(&irq_mis_count); > + irq_stat_inc_and_enable(IRQ_COUNT_IOAPIC_MISROUTED); > =C2=A0 eoi_ioapic_pin(cfg->vector, irq_data->chip_data); > =C2=A0 } > =C2=A0 > --- a/arch/x86/kernel/i8259.c > +++ b/arch/x86/kernel/i8259.c > @@ -214,7 +214,7 @@ static void mask_and_ack_8259A(struct ir > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "spurious 8259A interrupt: = IRQ%d.\n", irq); > =C2=A0 spurious_irq_mask |=3D irqmask; > =C2=A0 } > - atomic_inc(&irq_err_count); > + irq_stat_inc_and_enable(IRQ_COUNT_PIC_APIC_ERROR); > =C2=A0 /* > =C2=A0 * Theoretically we do not have to handle this IRQ, > =C2=A0 * but in Linux this does not cause problems and is > --- a/arch/x86/kernel/irq.c > +++ b/arch/x86/kernel/irq.c > @@ -39,8 +39,6 @@ EXPORT_PER_CPU_SYMBOL(__softirq_pending) > =C2=A0 > =C2=A0DEFINE_PER_CPU_CACHE_HOT(struct irq_stack *, hardirq_stack_ptr); > =C2=A0 > -atomic_t irq_err_count; > - > =C2=A0/* > =C2=A0 * 'what should we do if we get a hw irq event on an illegal vector= '. > =C2=A0 * each architecture has to answer this themselves. > @@ -124,6 +122,10 @@ static const struct irq_stat_info irq_st > =C2=A0#ifdef CONFIG_X86_POSTED_MSI > =C2=A0 ISS(POSTED_MSI_NOTIFICATION, "PMN", "=C2=A0 Posted MSI notificatio= n event\n"), > =C2=A0#endif > + IDS(PIC_APIC_ERROR, "ERR", "=C2=A0 PIC/APIC error interrupts\n"), > +#ifdef CONFIG_X86_IO_APIC > + IDS(IOAPIC_MISROUTED, "MIS", "=C2=A0 Misrouted IO/APIC interrupts\n"), > +#endif > =C2=A0}; > =C2=A0 > =C2=A0static DECLARE_BITMAP(irq_stat_count_show, IRQ_COUNT_MAX) __read_mo= stly; > @@ -183,10 +185,6 @@ int arch_show_interrupts(struct seq_file > =C2=A0 irq_proc_emit_counts(p, &irq_stat.counts[i]); > =C2=A0 seq_puts(p, info->text); > =C2=A0 } > - > - seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); > - if (IS_ENABLED(CONFIG_X86_IO_APIC)) > - seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count))= ; > =C2=A0 return 0; > =C2=A0} > =C2=A0 > @@ -202,12 +200,6 @@ u64 arch_irq_stat_cpu(unsigned int cpu) > =C2=A0 sum +=3D p->counts[i]; > =C2=A0 return sum; > =C2=A0} > - > -u64 arch_irq_stat(void) > -{ > - u64 sum =3D atomic_read(&irq_err_count); > - return sum; > -} > =C2=A0#endif /* CONFIG_PROC_FS */ > =C2=A0 > =C2=A0static __always_inline void handle_irq(struct irq_desc *desc, > --- a/fs/proc/stat.c > +++ b/fs/proc/stat.c > @@ -18,9 +18,6 @@ > =C2=A0#ifndef arch_irq_stat_cpu > =C2=A0#define arch_irq_stat_cpu(cpu) 0 > =C2=A0#endif > -#ifndef arch_irq_stat > -#define arch_irq_stat() 0 > -#endif > =C2=A0 > =C2=A0u64 get_idle_time(struct kernel_cpustat *kcs, int cpu) > =C2=A0{ > @@ -122,7 +119,6 @@ static int show_stat(struct seq_file *p, > =C2=A0 sum_softirq +=3D softirq_stat; > =C2=A0 } > =C2=A0 } > - sum +=3D arch_irq_stat(); > =C2=A0 > =C2=A0 seq_put_decimal_ull(p, "cpu=C2=A0 ", nsec_to_clock_t(user)); > =C2=A0 seq_put_decimal_ull(p, " ", nsec_to_clock_t(nice)); Reviewed-by: Radu Rendec