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([2a02:810d:15c0:828:cbf1:e7ef:fb81:e912]) by smtp.gmail.com with ESMTPSA id j2-20020aa7c402000000b00501c96564b5sm1491183edq.93.2023.05.03.23.30.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 May 2023 23:30:56 -0700 (PDT) Message-ID: <958cca71-b2f2-80af-541c-d1e84b151d3c@linaro.org> Date: Thu, 4 May 2023 08:30:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH v9 08/10] clk: nuvoton: Add clock driver for ma35d1 clock controller Content-Language: en-US To: Jacky Huang , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org, tmaimon77@gmail.com, catalin.marinas@arm.com, will@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang References: <20230504033726.93-1-ychuang570808@gmail.com> <20230504033726.93-9-ychuang570808@gmail.com> From: Krzysztof Kozlowski In-Reply-To: <20230504033726.93-9-ychuang570808@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/05/2023 05:37, Jacky Huang wrote: > From: Jacky Huang > > The clock controller generates clocks for the whole chip, including > system clocks and all peripheral clocks. This driver support ma35d1 > clock gating, divider, and individual PLL configuration. > > There are 6 PLLs in ma35d1 SoC: > - CA-PLL for the two Cortex-A35 CPU clock > - SYS-PLL for system bus, which comes from the companion MCU > and cannot be programmed by clock controller. > - DDR-PLL for DDR > - EPLL for GMAC and GFX, Display, and VDEC IPs. > - VPLL for video output pixel clock > - APLL for SDHC, I2S audio, and other IPs. > CA-PLL has only one operation mode. > DDR-PLL, EPLL, VPLL, and APLL are advanced PLLs which have 3 > operation modes: integer mode, fraction mode, and spread specturm mode. > > Signed-off-by: Jacky Huang > --- > drivers/clk/Makefile | 1 + > drivers/clk/nuvoton/Kconfig | 19 + > drivers/clk/nuvoton/Makefile | 4 + > drivers/clk/nuvoton/clk-ma35d1-divider.c | 140 ++++ > drivers/clk/nuvoton/clk-ma35d1-pll.c | 365 +++++++++ > drivers/clk/nuvoton/clk-ma35d1.c | 948 +++++++++++++++++++++++ Acked-by: Krzysztof Kozlowski Best regards, Krzysztof